• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• The Journal of Information Technology
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• v.12 no.2
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• pp.39-47
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• 2009

Residue Number System is used for the purpose of increasing the speed of processing in the many application parts of Image Processing, Computer Graphic, Neural Computing, Digital Signal Processing etc, since it has the characteristic of parallelism and no carry propagation at each moduli. DRNS has the twice RNS Conversion, it is used to decreases the size of the operator in RNS. But it has a week point on the Second Residue to First Residue Conversion time. So, in this paper SRTFR(Second Residue to First Residue) Converter using MRC(Mixed Radix Conversion) is designed to decrease the size of RTB(Residue to Binary) Converter. Since the proposed SRTFR Converter using MRC(Mixed Rdix Convertion) has a pipeline processing. Also, modular operation is applied to at each partitioned SAM(Subtraction and Addition) and MA(Multiplication and addition). In the following study, the more effective design on MA is needed.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.05a
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• pp.448-452
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• 2007

Many industrial operations require continuous or nearly-continuous operation of machines, which if interrupted can result in significant financial loss. The condition monitoring of these machines has received considerable attention recent years. Rapid developments in semiconductor, computing, and communication with a remote site have led to a new generation of sensor called "smart" sensors which are capable of wireless communication with a remote site. The purpose of this research is the development of smart sensor using which can on-line perform condition monitoring. This system is addressed to detect conditions that may lead to equipment failure when it is running. Moreover it will reduce condition monitoring expense using low cost MEMS accelerometer. This sensor can receive data in real-time or periodic time from MEMS accelerometer. Furthermore, this system is capable for signal preprocessing task (High Pass Filter, Low Pass Filter and Gain Amplifier) and analog to digital converter (A/D) which is controlled by CPU. A/D converter that converts 10bit digital data is used. This sensor communicates with a remote site PC using TCP/IP protocols. Wireless LAN contain IEEE 802.11i-PSK or WPA (PSK, TKIP) encryption. Developed sensor executes performance tests for data acquisition accuracy estimations.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.2018-2020
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• 1998

In design of a digital current controller for a 3$\phi$ voltage-source (VS) PWM converter, its conventional model, i.e., stationary or synchronous reference frame model, is used in obtaining its discretized version. It introduces, however, inherent errors since the following practical problems are not taken into consideration: the characteristics of the space vector-based pulsewidth modulation (SVPWM) and the time delays in the process of sampling and computation. In this paper, the new hybrid reference frame model of the 3$\phi$ VS PWM converter is proposed considering these problems. In addition, the direct digital current controller based on this model is designed without any prediction or extrapolation algorithm to compensate the time delay. So the control algorithm is made very simple. The validity of the proposed algorithm is proved by the computer simulation results.

• Journal of the Korean Society of Industry Convergence
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• v.6 no.1
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• pp.3-10
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• 2003

Application of matrix converter to vector control of induction motor using simplified Venturini algorithm which is capable of achieving the maximum output voltage is developed. This algorithm simplifies the control algorithm and therefor reduces the digital implementation time. Matrix converter is used as voltage-referenced voltage fed vector controlled induction motor drive. This paper describes the performance of vector controlled induction motor with four quadrant capability employing a matrix converter power circuit. The advantage of this system over the conventional rectifier-inverter arrangement are capability for regeneration into the utility, sinusoidal supply currents and minimum passive components. The steady-state and transient performance of the induction motor drive under the vector control technique is demonstrate with simulation and experiment results.

• Journal of Magnetics
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• v.17 no.2
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• pp.124-128
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• 2012

Many different converter topologies have been developed with a view to use the minimum number of switches in order to reduce construction costs. Among this research, the four-switch converter topology with a novel PWM control technique based on the current controlled PWM method is thought to be a good solution. In this paper, a two dimensional time-stepped voltage source finite-element method (FEM) is used to analyze the characteristics of a Flux-Reversal Machine (FRM) with a 4-switch converter. To validate the proposed computational method, a digital signal processor (DSP) installed controller and prototype FRM are built and experiments performed.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.477-484
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• 2013

This paper proposes a novel switching method of active clamp snubber for efficiency improvement of PV module integrated converter(MIC) system. Recently, MIC solar system is researched about the efficiency and safety. PV MIC system is used active clamp method of snubber circuit for the price and reliability of the system. But active clamp snubber circuit has the disadvantage that system efficiency is decreased for switch operating time because of heat loss of resonant between snubber capacitor and leakage inductance. To solve this problem, this paper proposes a novel switching method of the active clamp. The proposed method is a technique to reduce power consumption by reducing the resonance of the snubber switch operation time and through simulations and experiments proved the validity.

• 전자공학회논문지 IE
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• v.49 no.1
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• pp.1-6
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• 2012

For the performance improvement of a time-to-digital converter(TDC), a 2-stage high resolution TDC has been designed by using a 2-stage vernier time amplifier(2-S VTA). The two stage vernier time amplifier which has a gain over 64 of the resolution can enhance the resolution of the whole two stage TDC. Because of using a vernier TDC, the structure is not limited to advanced processes for achieving high resolution. The proposed TDC has been designed in a $0.18{\mu}m$ CMOS process and simulated with a 1.8V supply voltage. The entire input range is 512ps, and the full resolution 0.125ps.