• Journal of KIISE:Computer Systems and Theory
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• v.31 no.10
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• pp.553-561
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• 2004

Leader election is an important problem in developing fault-tolerant distributed systems. As a classic solution for leader election, there is Garcia-Molina's Bully Algorithm based on time-outs in synchronous systems. In this paper, we re-write the Bully Algorithm to use a failure detector instead of explicit time-outs. We show that this algorithm is more efficient than the Garcia-Molina's one in terms of the processing time. That is because the Bully_FD uses FD to know whether the process is up or down so fast and it speed up its execution time. Especially, where many processes are connected in the system and crash and recovery of processes are frequent, the Bully_FD algorithm is much more efficient than the classical Bully algorithm in terms of the processing time.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.106-115
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• 1994

This paper presents the design of a technology mapping system for optimizing delays of combinational and synchronous sequential logic circuits. The proposed system performs delay optimization for combinational logic circuits by remapping, buffering, and gate merging methods through the correct delay calculation in which the loading values are considered. To get time optimized synchronous sequential circuits, heuristic algorithms are proposed. The proposed algorithms reallocate registers by considering the critical path characteristics. Experimental results show that the proposed system produces a more optimized technology mapping for MCNC benchmarks compared with mis-II.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.299-304
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• 1998

An improved nonlinear speed control of a permanent magnet synchronous motor(PMSM) is presented. A quasi-linearized and decoupled model including the influence of parameter variations and speed measurement error on the nonlinear speed control of a PMSM is derived. Using this model, to overcome the drawbacks of conventional nonlinear control scheme, the improved nonlinear control scheme that employs time delay control(TDC) is proposed. To show the validity of the proposed control scheme, simulation studies are carried out and compared with the conventional control scheme.

• ETRI Journal
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• v.19 no.4
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• pp.326-343
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• 1997

In this paper, we propose an ATM switch with the rate more than gigabits per second to cope with future broadband service environments. The basic idea is to separate the connection control flow from the data information flow inside the switch. The proposed switch has a dual-plane switch matrix with the synchronous control algorithm. The queuing behaviors of the proposed switch are shown by the discrete-time queuing analysis. Numerical analyses are taken both in the non-blocking crossbar switch and the banyan switch with internal blocking. Results show that a proposed dual-plane $16{\times}16$ switch would have the acceptable performance with maximum throughput of about 95 percent.

• Journal of Power Electronics
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• v.14 no.1
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• pp.74-81
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• 2014

In this study, a brain emotional learning-based intelligent controller (BELBIC) is developed for the speed control of an interior permanent magnet synchronous motor (IPMSM). A novel and simple model of the IPMSM drive structure is established with the intelligent control system, which controls motor speed accurately without the use of any conventional PI controllers and is independent of motor parameters. This study is conducted in both real time and simulation with a new control plant for a laboratory 3 ph, 3.8 Nm IPMSM digital signal processor (DSP)-based drive system. This DSP-based drive system is then compared with conventional BELBIC and an optimized conventional PI controller. Results show that the proposed method performs better than the other controllers and exhibits excellent control characteristics, such as fast response, simple implementation, and robustness with respect to disturbances and manufacturing imperfections.

• Journal of Power Electronics
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• v.4 no.3
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• pp.180-187
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• 2004

This paper proposes a new control strategy for the dynamic voltage restorer (DVR). It is based on a synchronous PI decoupling control strategy which features fast response time and low steady state error. Therefore, the proposed control strategy produces faster action time against voltage sag and guarantees more than enough compensation for reduced supply voltage. Experimental results, implemented with the TMS320C3${\times}$DSP control unit, are shown to validate the effectiveness of the proposed control strategy.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.12
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• pp.93-100
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• 2013

This paper propose a method to design the rotor of synchronous reluctance motors(SynRM) for maximum torque and power factor by using DOE(design of experiment) with the design variables which are parameters of barriers and segments. In this process, there are problems that require lots of simulation time and number of simulations when calculating the both torque and power factor using the finite element method in order to find load angle, core loss per speed. In order to improve this problem, we calculate only value of flux linkage by finite element method, and can decrease analysis and the number of analysis time by applying steady state expression of the power factor and torque. Finally, in order to verify the characteristics of optimal model, we make prototype motor and compare with the conventional SynRM. In this experiment, we use the DC current decay test for calculating d-and q-axis inductance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.173-179
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• 2002

We propose a novel sensing circuit for 2T-2MTJ MRAM that can be used for high speed synchronous operation. Proposed bit-line sense amplifier detects small voltage difference in bit-lines and develops it into rail-to-rail swing while maintaining small voltage difference on TMR cells. It is small enough to fit into each column that the whole data array on selected word line are activated as in DRAMs for high-speed read-out by changing column addresses only. We designed a 256Kb read-only MRAM in a $0.35\mu\textrm{m}$ logic technology to verify the new sensing scheme. Simulation result shows a 25ns RAS access time and a cycle time shorter than 10 ns.

• Journal of The Korean Astronomical Society
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• v.51 no.1
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• pp.1-4
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• 2018

We study the pseudo-synchronous orbital motion of a binary system on the main sequence. The equations of the pseudo-synchronous orbit are derived up to $O(e^4)$ where e is the eccentricy of the orbit. We integrate the equations to present their solutions. The theoretical results are applied to the evolution of the orbit and spin of the binary star Y Cygni, which has a current eccentricity of $e_0\;=\;0.142$. We tabulate our numerical results for the evolution of the orbit and spin per century. The numerical results for the semi-major axes and rotational angular velocities in the evolutional time scales of three stages (synchronization, circularization, and collapse time scale) are also tabulated. Synchronization is achieved in about $5{\times}10^3\;years$ followed by circularization lasting about $1{\times}10^5\;years$ before decaying in $2{\times}10^5\;years$.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.67-69
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• 2007

PMSM (Permanent Magnet Synchronous Motor) current control is a most inner loop of electromechanical driving systems and it plays a foundation role in the hierarchy's control loop of several mechanical machine systems. In this paper, a simple RMRAC control scheme for the PMSM is proposed in the synchronous frame. In the synchronous current model, the input signal is composed of as a calculated voltage by adaptive laws and system disturbances. The gains of feed-forward and feed-back controller are estimated by the proposed e-modification methods respectively, where the disturbances are assumed as filtered current tracking errors. After the estimation of the disturbances from the tracking errors, the corresponding voltage is fed forward to control input to compensate for the disturbances. The proposed method is robust to high frequency disturbances and has a fast dynamic response to time varying reference current trajectory. It also shows a good real-time performance duo to it's simplicity of control structure. Through the simulations considering several cases of external disturbances and experimental results, efficiency of the proposed method is verified