• Korean journal of applied entomology
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• v.45 no.1 s.142
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• pp.31-36
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• 2006

Inflammation in the brain has known to be associated with the development of a various neurologiacal diseases. The hallmark of neuro-inflammation is the activation of microglia, brain macrophage. Pro-inflammatory compounds including nitric oxide(NO) are the main cause of neuro-degenerative disease such as Alzheimer's disease. In the study, we examined whether Harmonia axyridis extracts inhibit the NO production by a direct method using Griess reagent, western blotting and by RT-PCR(Reverse Transcription-Polymerase Chain Reactionin) the gene expression of inducible nitric oxide synthase(iNOS). Distilled water$(H_2O)$ and methanol(MeOH) extracts of H. axyridis inhibited the protein expression of TNF-a(Tumor Necrosis Factor) and IL-6(Interleukin) in LPS (Lipopolysaccharide) stimulated BV-2 cells at the concentration of 100 ng/ml. Incubation of BV-2 cells with the extracts of $H_2O$ of MeOH inhibited the LPS induced NO and iNOS protein. And this inhibition of iNOS protein is concordant with the inhibition of iNOS mRNA expression. These data suggested that H. axyridis extracts may play a crucial role in inhibiting the NO production.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.4
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• pp.17-27
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• 2007

The enhanced distributed channel access (EDCA) of IEEE 802.11e has been standardized for supporting Quality of Service (QoS) in wireless LANs. In the EDCA, support of QoS can be achieved statistically by reducing the probability of medium access for lower priority traffics. In other words, it provides statistical channel access rather than deterministically prioritized access to high priority traffic. Therefore, lower priority traffics affect the performance of higher priority traffics. Consequently, at the high loads, the EDCA does not guarantee the QoS of multimedia applications such as voice and video even though it provides higher priority. In this paper, we propose a simple and effective scheme, called deterministic priority channel access (DPCA), for improving the QoS performance of the EDCA mechanism. In order to provide guaranteed priority channel access to multimedia applications, the proposed scheme uses a busy tone for limiting the transmissions of lower priority traffics when higher priority traffic has data packets to send. Performance of the proposed scheme is investigated by numerical analysis and simulation. Our results show that the proposed scheme outperforms the EDCA in terms of throughput, delay, jitter, and drop under a wide range of contention levels.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.25-35
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• 1998

The control system architecture in switching systems have undergone numerous changes to provide various call processing capability needed in telecommunication services. During call processing in a distributed switching control environment, the delay effect due to communication among main processors or peripheral controllers is one of the limiting factors which affect the system performance. In this paper, we propose a performance model for an IPC(Inter Processor Communication) interface hardware block which is required on the ATM cell-based message processing in a distributed ATM exchange system, and analyze the primary causes which affect the processor performance through the simulation. Consequently, It can be shown that the local CPU of the several components(resources) related to the IPC scheme is a bottleneck factor in achieving the maximum system performance from the simulation results, such as the utilization of each processing component according to the change of the input message rate, and the queue length and processing delay according to input message rate. And we also give some useful results such as the maximum message processing capacity according to the change of the performance of local CPU, and the local CPU maximum throughput according to the change of average message length, which is applicable as a reference data for the improvement or expansion of the ATM control system.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.19-24
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• 2016

In Long Term Evolution-Advanced (LTE-A), small cell enhancement(SCE) has been developed as a cost-effective way of supporting exponentially increasing demand of wireless data services and satisfying the user quality of service(QoS). However, due to the dense and irregular distribution of a large number of small cells, the offloading scheme should be applied in the small cell network. In this paper, we propose an user offloading scheme for SCE in LTE-Advanced system. We divide the small cells into different clusters according to the reference signal received power(RSRP) from user equipment(UE). Within a cluster, We apply the user offloading scheme with the consideration of the number of users and interference conditions. Simulation results show that proposed scheme can improve the throughput, and spectral efficiency of small cell users. Eventually, proposed scheme can improve overall cell performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.13-18
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• 2016

In Long Term Evolution-Advanced (LTE-A), small cell enhancement(SCE) has been developed as a cost-effective way of supporting exponentially increasing demand of wireless data services and satisfying the user quality of service(QoS). However, there are many problems such as the transmission rate and transmission quality degradation due to the dense and irregular distribution of a large number of small cells. In this paper, we propose a clustering based interference management scheme in dense small cell network. We divide the small cells into different clusters according to the reference signal received power(RSRP) from user equipment(UE). Within a cluster, an almost blank subframe(ABS) is implemented to mitigate interference between the small cells. In addition, we apply the power control to reduce the interference between the clusters. Simulation results show that proposed scheme can improve Signal to Interference plus Noise Ratio(SINR), throughput, and spectral efficiency of small cell users. Eventually, proposed scheme can improve overall cell performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.22-31
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• 2015

Recently, 3rd Generation Partnership Project (3GPP) has developed device-to-device (D2D) communication to cope with the explosively increasing mobile data traffic. The D2D communication uses sidelink based on single carrier-frequency division multiple access (SC-FMDA) due to its low peak-to-average power ratio (PAPR). In addition, demodulation reference signal (DMRS) is designed to support multiple input multiple output (MIMO). In this paper, we propose the DFT-based channel estimation scheme for sidelink in D2D communication. The proposed scheme uses the 2-Dimensional Minimum Mean Square Error (2-D MMSE) interpolation scheme for the user moving at a high speed. We perform the system level simulation based on 20MHz bandwidth of 3GPP LTE-Advanced system. Simulation results show that the proposed channel estimation scheme can improve signal-to-interference-plus-noise ratio (SINR), throughput and spectral efficiency of conventional scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• The KIPS Transactions:PartC
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• v.12C no.6 s.102
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• pp.781-792
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• 2005

This study proposes an Architecture for user level End-to-end Quality of Service(QoS) using overlay In Next Generation Network(NGN). Inexisting NGNs, the IMS of a control plane provides user QoS through direct traffic control and resource-reservation over the IP packet transport network of a user plane. Further, a set of torrent studies are ongoing not only to maximize the QoS for users, but also to minimize the quality deterioration for supporting the user End-to-end QoS. Along with that, an extended QoS in user level must be considered, for Instance, differentiating service quality to support users' expectation, providing optimized contents by users' equipments, and so forth. Accordingly, the Overlay Service Network Architecture proposed by this study provides protocol adaptation for maximum throughput on transport layer by using the most efficient transport layer protocol to various network circumstances. Also, the Overlay Service Network Architecture on application layer distributes processing delay from the data transformation process of the user equipment to the network, and it is capable of intermediate processing depending on user service level. application service feature, and equipment circumstance as well. Thus, this study mainly proposes the Overlay Service Network Architecture for user level end-to-end QoS in NGN with the quality control features both on the transport layer and the application layer, an internal component feature, and a service scenario providing the QoS linking with 3GPP.