• KEPCO Journal on Electric Power and Energy
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• v.5 no.1
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• pp.39-43
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• 2019

Hydrogen energy has positive effects as an alternative energy source to overcome the energy shortage issues. On the other hand, since stability is very important in use, sensor technology that enables accurate and rapid detection of hydrogen gas is highly required. In this study, hydrogen sensor was developed on AlGaN/GaN heterostructure platform using Pd catalyst where a recess structure was employed to improve the sensitivity. Temperature and bias voltage dependencies on sensitivity were carefully investigated using a hydrogen concentration of 4% that is the safety threshold concentration. Due to the excellent properties of AlGaN/GaN heterostructure in conjunction with the recess structure, a very high sensitivity of 56% was achieved with a fast response speed of 0.75 sec.

• Korean Journal of Metals and Materials
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• v.49 no.4
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• pp.342-347
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• 2011

We fabricated the silicon nanodots using the low pressure chemical vapor deposition technique to investigate their electron field emission characteristics. Atomic force microscope measurements performed for the silicon nanodot samples having various process parameters, such as, deposition time and deposition pressure, revealed that the silicon nanodots with an average size of 20 nm, height of 5 nm, and density of $1.3\;{\times}\;10^{11}\;cm^{-2}$ were easily formed. Electron field emission measurements were performed with the silicon nanodot layer as the cathode electrode. The current-voltage curves revealed that the threshold electric field was as low as $8.3\;V/{\mu}m$ and the field enhancement factor reached as large as 698, which is compatible with the silicon cathode tips fabricated by other techniques. These electron field emission results point to the possibility of using a silicon-based light source for display devices.

• Korean Journal of Metals and Materials
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• v.48 no.3
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• pp.256-261
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• 2010

In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.

• Journal of Sensor Science and Technology
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• v.30 no.6
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• pp.436-440
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• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• Biomolecules & Therapeutics
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• v.31 no.2
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• pp.168-175
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• 2023

Tramadol is an opioid analog used to treat chronic and acute pain. Intradermal injections of tramadol at hundreds of millimoles have been shown to produce a local anesthetic effect. We used the whole-cell patch-clamp technique in this study to investigate whether tramadol blocks the sodium current in HEK293 cells, which stably express the pain threshold sodium channel Na_v1.7 or the cardiac sodium channel Na_v1.5. The half-maximal inhibitory concentration of tramadol was 0.73 mM for Na_v1.7 and 0.43 mM for Na_v1.5 at a holding potential of -100 mV. The blocking effects of tramadol were completely reversible. Tramadol shifted the steady-state inactivation curves of Na_v1.7 and Na_v1.5 toward hyperpolarization. Tramadol also slowed the recovery rate from the inactivation of Na_v1.7 and Na_v1.5 and induced stronger use-dependent inhibition. Because the mean plasma concentration of tramadol upon oral administration is lower than its mean blocking concentration of sodium channels in this study, it is unlikely that tramadol in plasma will have an analgesic effect by blocking Na_v1.7 or show cardiotoxicity by blocking Na_v1.5. However, tramadol could act as a local anesthetic when used at a concentration of several hundred millimoles by intradermal injection and as an antiarrhythmic when injected intravenously at a similar dose, as does lidocaine.

• Korean Journal of Materials Research
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• v.33 no.11
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• pp.491-496
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• 2023

As the demand for p-type semiconductors increases, much effort is being put into developing new p-type materials. This demand has led to the development of novel new p-type semiconductors that go beyond existing p-type semiconductors. Copper iodide (CuI) has recently received much attention due to its wide band gap, excellent optical and electrical properties, and low temperature synthesis. However, there are limits to its use as a semiconductor material for thin film transistor devices due to the uncontrolled generation of copper vacancies and excessive hole doping. In this work, p-type CuI semiconductors were fabricated using the chemical vapor deposition (CVD) process for thin-film transistor (TFT) applications. The vacuum process has advantages over conventional solution processes, including conformal coating, large area uniformity, easy thickness control and so on. CuI thin films were fabricated at various deposition temperatures from 150 to 250 ℃ The surface roughness root mean square (RMS) value, which is related to carrier transport, decreases with increasing deposition temperature. Hall effect measurements showed that all fabricated CuI films had p-type behavior and that the Hall mobility decreased with increasing deposition temperature. The CuI TFTs showed no clear on/off because of the high concentration of carriers. By adopting a Zn capping layer, carrier concentrations decreased, leading to clear on and off behavior. Finally, stability tests of the PBS and NBS showed a threshold voltage shift within ±1 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.6
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• pp.588-593
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• 2023

The advantage of OTFT technology is that large-area circuits can be manufactured on flexible substrates using a low-cost solution process such as inkjet printing. Compared to silicon-based inorganic semiconductor processes, the process temperature is lower and the process time is shorter, so it can be widely applied to fields that do not require high electron mobility. Materials that have utility as electrode materials include carbon that can be solution-processed, transparent carbon thin films, and metallic nanoparticles, etc. are being studied. Recently, a technology has been developed to facilitate charge injection by coating the surface of the Al electrode with solution-processable titanium oxide (TiOx), which can greatly improve the performance of OTFT. In order to commercialize OTFT technology, an appropriate method is to use a complementary circuit with excellent reliability and stability. For this, insulators and channel semiconductors using organic materials must have stability in the air. In this study, carbon-doped Mo (MoC) thin films were fabricated with different graphite target power densities via unbalanced magnetron sputtering (UBM). The influence of graphite target power density on the structural, surface area, physical, and electrical properties of MoC films was investigated. MoC thin films deposited by the unbalanced magnetron sputtering method exhibited a smooth and uniform surface. However, as the graphite target power density increased, the rms surface roughness of the MoC film increased, and the hardness and elastic modulus of the MoC thin film increased. Additionally, as the graphite target power density increased, the resistivity value of the MoC film increased. In the performance of an organic thin film transistor using a MoC gate electrode, the carrier mobility, threshold voltage, and drain current on/off ratio (I_on/I_off) showed 0.15 cm²/V·s, -5.6 V, and 7.5×10⁴, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• ETRI Journal
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• v.38 no.4
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• pp.675-684
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• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.