• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.71-81
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• 2014

In this paper, the performance variations of tri-gate FinFET are analyzed for different fin shapes and source/drain epitaxy types using a 3D device simulator(Sentaurus). If the fin shape changes from a rectangular shape to a triangular shape, the threshold voltage increases due to a non-uniform potential distribution, the off-current decreases by 72.23%, and the gate capacitance decreases by 16.01%. In order to analyze the device performance change from the structural change of the source/drain epitaxy, we compared the grown on the fin (grown-on-fin) structure and grown after the fin etch (etched-fin) structure. 3-stage ring oscillator was simulated using Sentaurus mixed-mode, and the energy-delay products are derived for the different fin and source/drain shapes. The FinFET device with triangular-shaped fin with etched-fin source/drain type shows the minimum the ring oscillator delay and energy-delay product.

• Bulletin of the Korean Chemical Society
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• v.28 no.11
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• pp.1945-1950
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• 2007

Two fluorene-based conjugated copolymers containing hexyl-thiophene derivatives, PF-1T and PF-4T, were synthesized via the palladium-catalyzed Suzuki coupling reaction. The number-average molecular weights (Mn) of PF-1T and PF-4T were found to be 19,100 and 13,200, respectively. These polymers were soluble in common organic solvents such as chloroform, chlorobenzene, toluene, etc. The UV-vis absorption maximum peaks of PF-1T and PF-4T in the film state were found to be 410 nm and 431 nm, respectively. Electrochemical characterization revealed that these polymers have low highest occupied molecular orbital (HOMO) levels, indicating good resistance against oxidative doping. Thin film transistor devices were fabricated using the top contact geometry. PF-1T showed much better thin-film transistor performance than PF-4T. A thin film of PF- 1T gave a saturation mobility of 0.001-0.003 cm2 V?1 s?1, an on/off ratio of 1.0 × 105, and a small threshold voltage of ?8.3 V. To support TFT performance, we carried out DSC, AFM, and XRD measurements.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.16.1-16.1
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• 2009

We have fabricated solution processed oxide semiconductor active layer for thin film transistors (TFTs). The oxide semiconductor layers were prepared by ink-jet printing the sol-gel precursor solution based on doped-ZnO. Inorganic ZnO-based thin films have drawn significant attention as an active channel layer for TFTs applications alternative to conventional Si-based materials and organic semiconducting materials, due to their wide energy band gap, optical transparency, high mobility, and better stability. However, in spite of such excellent device performances, the fabrication methods of ZnO related oxide active layer involve high cost vacuum processes such as sputtering and pulsed laser deposition. Herein we introduced the ink-jet printing technology to prepare the active layers of oxide semiconductor. Stable sol-gel precursor solutions were obtained by controlling the composition of precursor as well as solvents and stabilizers, and their influences on electrical performance of the transistors were demonstrated by measuring electrical parameters such as off-current, on-current, mobility, and threshold voltage. Microstructure and thermal behavior of the doped ZnO films were investigated by SEM, XRD, and TG/DTA. Furthermore, we studied the influence of the ink-jet printing conditions such as substrate temperature and surface treatment on the microstructure of the ink-jet printed active layers and electrical performance. The mobility value of the device with optimized condition was about 0.1-1.0 $cm^2/Vs$ and the on/off current ratio was about $10^6$. Our investigations demonstrate the feasibility of the ink-jet printed oxide TFTs toward successful application to cost-effective and mass-producible displays.

• Journal of the Korean Magnetics Society
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• v.9 no.6
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• pp.301-305
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• 1999

NiFe(60$\AA$)/Co(5$\AA$)/Cu(60$\AA$)/Co(30$\AA$) spin valve thin films were patterned into magnetoresistive random access memory (MRAM) cells by a conventional optical lithography process and their output and switching properties were characterized with respect to the cell size and geometry. When 1 mA of constant sense current was applied to the cells, a few or a few tens of mV of output voltage was measured within about 30 Oe of external magnetic field, which is an adequate output property for the commercializing of competitive MRAM devices. In order to resolve the problem of increase in the switching thresholds of magnetic layers with the downsizing of MRAM cells, a new approach using the controlled shape anisotropy was suggested and interpreted by a simple calculation of anisotropy energies of magnetic layers consisting of the cells. This concept gave a reduced switching threshold in NiFe(60$\AA$)/Co(5$\AA$) layer consisting of the patterned cells from about 15 Oe to 5 Oe and it was thought that this concept would be much helpful for the realization of competitive MRAM devices.

• Transactions on Electrical and Electronic Materials
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• v.6 no.2
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• pp.73-77
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• 2005

In this study, we investigated response characteristics of liquid crystal display (LCD) with different operating mode of nematic liquid crystals (NLCs) such as 45 $^{circ} twisted nematic (TN), 67.3 $^{circ} TN and electrical controlled birefringence (ECB) on the rubbed polyimide (PI) surface with side chains. The pretilt angles generated on polyimide surfaces of the three kinds of LCD operating modes were about 12 $^{circ} that was higher than those of conventional TN-LCOs. Also, the Electro-optical (EO) performance of these LCOs showed stable condition. Low transmittance of the 45 $^{circ} TN and 67.3 $^{circ} TN cell on the rubbed PI surface were measured by using low cell gap d. The fast response time in ECB cell among the three kinds of LCD operating modes was achieved. Also, thermal ability of fast 90 $^{circ} TN-LCD was investigated. The threshold voltage and the response time of thermal stressed TN-LCOs showed the same performances on no thermal stressed TN-LCOs. There was little change of value in these TN cells. However, the transmittances of TN-LCOs on the rubbed PI surface decreased while increasing thermal stress time. Therefore, the thermal stability of TN-LCD was decreased by the high thermal stress for the long duration.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.6
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• pp.229-235
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• 2002

This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.9
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• pp.835-843
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• 2008

We have fabricated the source-drain electrodes for OTFTs by screen printing method and manufactured Ag pastes as conductive paste. To obtain excellent conductivity and screen-printability of Ag pastes, the dispersion characteristics of Ag pastes prepared from two types of acryl resins with different molecular structures and Ag powder treated with caprylic acid, triethanol amine and dodecane thiol as surfactant respectively were investigated. The Ag pastes containing Ag powder treated with dodecane thiol having thiol as anchor group or AA4123 with carboxyl group(COOH) of hydrophilic group as binder resin exhibited excellent dispersity. But, Ag pastes(CA-41, TA-41, DT-41) prepared from AA4123 fabricated the insulating layer since the strong interaction between surface of Ag powder and carboxyl group(COOH) of AA4123 interfered with the formation of conduction path among Ag powders. The viscosity behavior of Ag pastes exhibited shear-thinning flow in the high shear rate range and the pastes with bad dispersion characteristic demonstrated higher shear-thinning index than those with good dispersity due to the weak flocculated network structure. The output curve of OTFT device with a channel length of 107 ${\mu}m$ using screen-printed S-D electrodes from DT-30 showed good saturation behavior and no significant contact resistance. And this device exhibited a saturation mobility of $4.0{\times}10^{-3}$ $cm^2/Vs$, on/off current ratio of about $10^5$ and a threshold voltage of about 0.7 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.8
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• pp.469-473
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• 2017

We investigated the effect of different thin-film thicknesses (25, 30, and 40 nm) on the electrical performance of solution-processed indium-zinc-oxide (IZO) thin-film transistors (TFTs). The structural properties of the IZO thin films were investigated by atomic force microscopy (AFM). AFM images revealed that the IZO thin films with thicknesses of 25 and 40 nm exhibit an uneven distribution of grains, which deforms the thin film and degrades the performance of the IZO TFT. Further, the IZO thin film with a thickness of 30 nm exhibits a homogeneous and smooth surface with a low RMS roughness of 1.88 nm. The IZO TFTs with the 30-nm-thick IZO film exhibit excellent results, with a field-effect mobility of $3.0({\pm}0.2)cm^2/Vs$, high Ion/Ioff ratio of $1.1{\times}10^7$, threshold voltage of $0.4({\pm}0.1)V$, and subthreshold swing of $0.7({\pm}0.01)V/dec$. The optimization of oxide semiconductor thickness through analysis of the surface morphologies can thus contribute to the development of oxide TFT manufacturing technology.