• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1590-1592
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• 2002

In this work the electrical characteristics of organic TFTs using organic insulator and flexible polyester substrate have been investigated. Pentacene and PVP(polyvinylphenol) are used as an active semiconducting layer and dielectric layer respectively. Pentacene was thermally evaporated in vacuum at a pressure of about $1{\times}10^{-6}$ Torr and at a deposition rate of $0.5{\AA}$/sec, and PVP was spin-coated. Aluminium and gold were used for gate and source/drain electrodes. 0.1mm thick flexible polyester substrate was used instead of glass or silicon wafer.

• Journal of Sensor Science and Technology
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• v.14 no.4
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• pp.219-224
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• 2005

In this paper, a contact-type linear encoder-like capacitive displacement sensor (CLECDS) is proposed. It is based on the linear encoder capacitive displacement sensor that consists of two substrates with a series of conducting grating in identical size and it is used as a contact sensor of which the two substrates assembled faced to each other after coated with thin dielectric film. It was confirmed that the prototype of this sensor has resolution of about 126nm and measuring range of 20 mm in the test.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.11a
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• pp.155-155
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• 2015

메모리 반도체의 지속적인 scale down을 위해서는 고유전 산화막을 이용한 등가산화막두께(EOT) 스케일링이 이뤄져야 한다. 특히, DRAM의 커패시터의 경우, EOT scaling을 위한 신 물질 및 공정개발이 지연되면서 전극과 유전체 사이의 계면특성 개선, 또는 기존에 사용하던 물질을 지속적으로 사용할 수 있는 방안에 대한 필요성이 대두되고 있다. 본 발표에서는 DRAM 커패시터 소재 개발이 겪고 있는 어려움에 대해 소개하고 기존에 반도체 라인에서 사용하고 있는 물질들을 조합한 다성분계 산화막을 이용하여 EOT 0.5 nm를 구현하기 위한 연구 결과에 대해 보고한다. 또한 앞으로 지속적인 커패시터 유전체 개발을 위해 관심을 갖고 수행해야 하는 연구에 대해 함께 다룬다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.1019-1023
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• 2005

We have examined the electrical and optical characteristics of the plasma display panel produced by vacuum in-line sealing technology. In the MgO layer deposited at room temperature, after sealing at the panel temperature of $430^{\circ}C$, the luminous efficiency decreased compared with that of the panel before sealing. Moreover, firing and sustain voltage of the sealed panel increased compared with that of the panel before sealing. This was resulted from that the MgO protective layer was cracked by the softening of the dielectric layer during the sealing process. In order to avoid the MgO crack during the vacuum in-line sealing, thermally stable MgO layer or lower temperature sealing is required.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.428-431
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• 2002

Recently, the study on development of electrical and electronic device is done to get miniature, high degrees of integration and efficiency by using inorganic materials. the study of Langmuir-Boldgett(LB) method that uses organic materials because of the limitation for the ultrasmall size. The structure of MIM(Metal-Insulator-Metal) device is Cr-Au/ PBLG/ Al. the number of accumulated layers are 1, 3, 5, 7, 9. The I-V characteristic of the device is measured from 0[V] to 2[V] and the characteristic of current-time of the devices. We have investigated the capacitance because PBLG system have a accumulated layers the maximum value of measured current is increased as the number of accumulated layers are decreased. The capacitor properties of a thin film is better as the distance between electrodes is smaller. The results have shown the insulating materials and could control the conductivity by accumulated layers.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.227-229
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• 2002

In this paper, we report on a microstrip line voltage controlled tunable bandpass filter. We used the characteristic the relative dielectric constant of thin film ferroelectrics depends on the applied dr voltage. we designed using Au/BSTO/MgO/Au structure. We cascaded many resonators for large furling range sustaining 1 GHz renter frequency, narrow band, low IL ($\leq$4 dB). We could design the BPF of which center frequency is 16 GHz, 1.9 GHz tuning range, the narrow bandwidth within 800 MHz, low insertion loss less than 3 dB by adjusting the gap of 3 cascaded resonators.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.86-87
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• 2007

The dispersive method of white-light interferometry is proper for in-line 3-D inspection of dielectric thin-film thickness to be used in the semiconductor and flat-panel display industry. This research is the measurement application of CMP patterned wafer. The results describe 3-D and 2-D profile of the step height during polishing time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.755-758
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• 2000

YMnO$_3$films have been deposited with different Rf powers of 60W, 80W, 100W, and 120W. The structural properties of YMnO$_3$films on Si(100) were analysed by XRD(X-ray diffraction). The c-axis oriented peaks of YMnO$_3$were observed deposited in YMnO$_3$/Si(100) structure of RF power at 87$0^{\circ}C$ in oxygen ambient, and the peaks were enlarged by increasing The RF powers. The dielectric constant of the film deposited at 100W and 120W of RF power were about 19, 20 respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.313-316
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• 2004

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics(ILD). we investigated the performance of $WO_3$ CMP used silica slurry, ceria slurry, tungsten slurry In this paper, the effects of addition oxidizer on the $WO_3$ CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity.