• 제목/요약/키워드: Thin plastic substrate

검색결과 111건 처리시간 0.033초

저온배향막을 이용한 Flexible 액정디스플레이의 액정 배향 효과 (Liquid Crystal Alignment Effect of Flexible Liquid Crystal Display with Low Temperature Alignment Layer)

  • 황정연;남기형;김종환;김강우;서대식;서동학
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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    • pp.199-202
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    • 2003
  • We have investigated the generation of pretilt angle for a nematic liquid crystal (NLC) alignment with rubbing alignment method on two kinds of polyimide (PI) surfaces using thin plastic substrates. The generated NLC pretilt angles on the pre-imidized type PI are about $3.8^{\circ}$ by the rubbing alignment method with thin plastic substrates, However, the pretilt angle measured at about $2.8^{\circ}$ lower on the polyamic acid type PI than by pre-imidized type PI surface with thin polymer film. The tilt angle increases as increasing curring temperature for making polyimide layer using polyamic acid type PI. It was concluded that pretilt angle in the polyimide surface is attributable to the increasing of imide rato.

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고유전율 절연체를 활용한 저 전압 유연 유기물 박막 트랜지스터 (Low-voltage Organic Thin-film Transistors with Polymeric High-k Gate Insulator on a Flexible Substrates)

  • 김재현;배진혁;이인호;김민회
    • 센서학회지
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    • 제24권3호
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    • pp.165-168
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    • 2015
  • We demonstrated low-voltage organic thin-film transistors (OTFTs) with bilayer insulators, high-k polymer and low temperature crosslinkable polymer, on a flexible plastic substrate. Poly (vinylidene fluoridetrifluoroethylene) (P(VDF-TrFE)) and poly (2-vinylnaphthalene) are used for high-k polymer gate insulator and low temperature crosslinkable polymer insulators, respectively. The mobility of flexible OTFTs is $0.17cm^2/Vs$ at gate voltages -5 V after bending operation.

3.5-Inch QCIF AMOLED Panels with Ultra-low-Temperature Polycrystalline Silicon Thin Film Transistor on Plastic Substrate

  • Kim, Yong-Hae;Chung, Choong-Heui;Moon, Jae-Hyun;Lee, Su-Jae;Kim, Gi-Heon;Song, Yoon-Ho
    • ETRI Journal
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    • 제30권2호
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    • pp.308-314
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    • 2008
  • In this paper, we describe the fabrication of 3.5-inch QCIF active matrix organic light emitting display (AMOLED) panels driven by thin film transistors, which are produced by an ultra-low-temperature polycrystalline silicon process on plastic substrates. The over all processing scheme and technical details are discussed from the viewpoint of mechanical stability and display performance. New ideas, such as a new triple-layered metal gate structure to lower leakage current and organic layers for electrical passivation and stress reduction are highlighted. The operation of a 3.5-inch QCIF AMOLED is also demonstrated.

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투명 전자 소자로의 응용을 위해 플라스틱 기판에 성장시킨 ZnO 특성 (Characteristic of ZnO Thin Film Grown on Plastic Substrates for the Application of Transparent Electronic Devices)

  • 이준표;윤영섭;강성준
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2008년도 하계종합학술대회
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    • pp.503-504
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    • 2008
  • ZnO thin films were deposited on glass and plastic substrates at different $Ar/O_2$ gas flow ratio in RF magnetron sputtering system. To investigate structural and optical properties of ZnO thin films, X-ray Diffactometer and UV-Vis Spectrometer were performed, respectively. The obtained films showed a preferred orientation the c-axis perpendicular to the substrate and transmittance above 80 % in visible range.

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저온 열처리 공정에 따른 Ag2Se 나노입자 박막의 열전특성 (Effect of Annealing Temperature on Thermoelectric Properties of Ag2Se Nanoparticle Thin Films)

  • 양승건;조경아;윤정권;최진용;김상식
    • 전기학회논문지
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    • 제65권4호
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    • pp.611-616
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    • 2016
  • In this study, we synthesized $Ag_2Se$ nanoparticles (NPs) in an aqueous solution and investigated the thermoelectric characteristics of $Ag_2Se$ NPs thin films on plastic substrates. Regardless of thermal annealing treatment, all the $Ag_2Se$ NPs thin films show the negative Seebeck coefficients, indicating the n-type characteristics. As the annealing temperature increases, the electric conductivity increases while the Seebeck coefficient decreases. The electric conductivity of the thin film annealed at $180^{\circ}C$ is larger by $10^6$ times, compared with the as-prepared thin film, And the maximum power density for the thin film annealed at $180^{\circ}C$ is calculated to be $44{\mu}W/cm^2$.

Low temperature pulsed ion shower doping for poly-Si TFT on plastic

  • Kim, Jong-Man;Hong, Wan-Shick;Kim, Do-Young;Jung, Ji-Sim;Kwon, Jang-Yeon;Noguchi, Takashi
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.95-97
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    • 2004
  • We studied a low temperature ion doping process for poly-Si Thin Film Transistor (TFT) on plastic substrates. The ion doping process was performed using an ion shower system, and subsequently, excimer laser annealing (ELA) was done for the activation. We have studied the crystallinity of Si surface at each step using UV-reflectance spectroscopy and the sheet resistance using 4-point probe. We found that the temperature has increased during ion shower doping for a-Si film and the activation has not been fulfilled stably because of the thermal damage against the plastic substrate. By trying newly a pulsed ion shower doping, the ion was efficiently incorporated into the a-Si film on plastic substrate. The sheet resistance decreased with the increase of the pulsed doping time, which was corresponded to the incorporated dose. Also we confirmed a relationship between the crystallinity and the sheet resistance. A sheet resistance of 300 ${\Omega}$/sq for the Si film of 50nm thickness was obtained with a good reproducibility. The ion shower technique is a promising doping technique for ultra low temperature poly-Si TFTs on plastic substrates as well as those on glass substrates.

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Electrophoretic Display employing OTFT-Backplane on plastic substrate

  • Ryu, Gi-Seong;Lee, Myung-Won;Song, Chung-Kun
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.1178-1181
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    • 2006
  • We fabricated a flexible OTFT(organic thin film transistor) backplane for the electrophoretic display. The backplane was composed of $128{\times}96pixels$ on the Polyethylene Naphthalate substrate in which each pixel had one OTFT. The OTFTs employed bottom contact structure and used the cross-linked polyvinylphenol for gate insulator and pentacene for active layer

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Nano Pillar Array 사출성형을 이용한 DNA 분리 칩 개발 (Development of the DNA Sequencing Chip with Nano Pillar Array using Injection Molding)

  • 김성곤;최두선;유영은;제태진;김태훈;황경현
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2005년도 춘계학술대회 논문집
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    • pp.1206-1209
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    • 2005
  • In recent, injection molding process for features in sub-micron scale is under active development as patterning nano-scale features, which can provide the master or stamp for molding, and becomes available around the world. Injection molding has been one of the most efficient processes for mass production of the plastic product, and this process is already applied to nano-technology products successfully such as optical storage media like DVD or BD which is a large area plastic thin substrate with nano-scale features on its surface. Bio chip for like DNA sequencing may be another application of this plastic substrate. The DNA can be sequenced using order of 100 nm pore structure when making the DNA flow through the pore structure. Agarose gel and silicon based chip have been used to sequence the DNA, but injection molded plastic chip may have benefit in terms of cost. This plastic DNA sequencing chip has plenty of pillars in order of 100 nm in diameter on the substrate. When the usual features in case of DVD or BD have very low aspect ratio, even less than 0.5, but the DNA chip will have relatively high aspect ratio of about 2. It is not easy to injection mold the large area thin substrate with sub-micron features on its surface due to the characteristics of the molding process and it becomes much more difficult when the aspect ratio of the features becomes high. We investigated the effect of the molding parameters for injection molding with high aspect ratio nano-scale features and injection molded some plastic DNA sequencing chips. We also fabricated PR masters and Ni stamps of the DNA chip to be used for molding

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Development of a Low Temperature Doping Technique for Applications in Poly-Si TFT on Plastic Substrates

  • Hong, Wan-Shick;Kim, Jong-Man
    • Journal of Information Display
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    • 제4권3호
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    • pp.17-21
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    • 2003
  • A low temperature doping technique to be applied in poly-Si TFTs on plastic substrates was investigated. Heavily-doped amorphous silicon layers were deposited on poly-Si and the dopant atoms were driven in by subsequent excimer laser annealing. The entire process was carried out under a substrate temperature of 120 $^{\circ}C$, and a sheet resistance of as low as 300 ${\Omega}$/sq. was obtained.

Study of Magnetic Field Shielded Sputtering Process as a Room Temperature High Quality ITO Thin Film Deposition Process

  • Lee, Jun-Young;Jang, Yun-Sung;Lee, You-Jong;Hong, Mun-Pyo
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.288-289
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    • 2011
  • Indium Tin Oxide (ITO) is a typical highly Transparent Conductive Oxide (TCO) currently used as a transparent electrode material. Most widely used deposition method is the sputtering process for ITO film deposition because it has a high deposition rate, allows accurate control of the film thickness and easy deposition process and high electrical/optical properties. However, to apply high quality ITO thin film in a flexible microelectronic device using a plastic substrate, conventional DC magnetron sputtering (DMS) processed ITO thin film is not suitable because it needs a high temperature thermal annealing process to obtain high optical transmittance and low resistivity, while the generally plastic substrates has low glass transition temperatures. In the room temperature sputtering process, the electrical property degradation of ITO thin film is caused by negative oxygen ions effect. This high energy negative oxygen ions(about over 100eV) can be critical physical bombardment damages against the formation of the ITO thin film, and this damage does not recover in the room temperature process that does not offer thermal annealing. Hence new ITO deposition process that can provide the high electrical/optical properties of the ITO film at room temperature is needed. To solve these limitations we develop the Magnetic Field Shielded Sputtering (MFSS) system. The MFSS is based on DMS and it has the plasma limiter, which compose the permanent magnet array (Fig.1). During the ITO thin film deposition in the MFSS process, the electrons in the plasma are trapped by the magnetic field at the plasma limiters. The plasma limiter, which has a negative potential in the MFSS process, prevents to the damage by negative oxygen ions bombardment, and increases the heat(-) up effect by the Ar ions in the bulk plasma. Fig. 2. shows the electrical properties of the MFSS ITO thin film and DMS ITO thin film at room temperature. With the increase of the sputtering pressure, the resistivity of DMS ITO increases. On the other hand, the resistivity of the MFSS ITO slightly increases and becomes lower than that of the DMS ITO at all sputtering pressures. The lowest resistivity of the DMS ITO is $1.0{\times}10-3{\Omega}{\cdot}cm$ and that of the MFSS ITO is $4.5{\times}10-4{\Omega}{\cdot}cm$. This resistivity difference is caused by the carrier mobility. The carrier mobility of the MFSS ITO is 40 $cm^2/V{\cdot}s$, which is significantly higher than that of the DMS ITO (10 $cm^2/V{\cdot}s$). The low resistivity and high carrier mobility of the MFSS ITO are due to the magnetic field shielded effect. In addition, although not shown in this paper, the roughness of the MFSS ITO thin film is lower than that of the DMS ITO thin film, and TEM, XRD and XPS analysis of the MFSS ITO show the nano-crystalline structure. As a result, the MFSS process can effectively prevent to the high energy negative oxygen ions bombardment and supply activation energies by accelerating Ar ions in the plasma; therefore, high quality ITO can be deposited at room temperature.

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