• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.85-89
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• 2014

We propose the new fabrication method of a 70 nm half-pitch wire grid polarizer with high performance using magnetic soft mold. The device is a form of aluminium gratings on a PET(Polyethylene phthalate) substrate whose size of $3cm{\times}3cm$ is compatible with a TFT_LCD(Tin Flat Transistor Liquid Crystal Display) panel. A magnetic soft mold with a pitch of 70 nm is fabricated using two-step replication method. As a result, we get a NWGP pattern which has 70.39 nm line width, 64.76 nm depth, 140.78 nm pitch, on substrate. The maximum and minimum transmittances of the NWGP at 800 nm are 75% and 10%, respectively. This work demonstrates a unique cost-effective solution for nanopatterning requirements in consumer electronics components.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.3.2-3.2
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• 2011

In recent years, inkjet printing technology has received significant attention as a micro/nanofabrication technique for flexible printing of electronic circuits and solar cells, as well for biomaterial patterning. It eliminates the need for physical masks, causes fewer environment problems, lowers fabrication costs, and offers good layer-to-layer registration. To fulfill the requirements for use in the above applications, however, the inkjet system must meet certain criteria such as high frequency jetting, uniform droplet size, high density nozzle array, etc. Existing inkjet devices are either based on thermal bubbles or piezoelectric pumping; they have several drawbacks for flexible printing. For instance, thermal bubble jetting has limitations in terms of size and density of the nozzle array as well as the ejection frequency. Piezoelectric based devices suffer from poor pumping energy in addition to inadequate ejection frequency. Recently, an electrohydrodynamic (EHD) printing technique has been suggested and proposed as an alternative to thermal bubble or piezoelectric devices. In EHD jetting, a liquid (ink) is pumped through a nozzle and a strong electric field is applied between the nozzle and an extractor plate, which induce charges at the surfaces of the liquid meniscus. This electric field creates an electric stress that stretches the meniscus in the direction of the electric field. Once the electric field force is larger than the surface tension force, a liquid droplet is formed. An EHD inkjet head can produce droplets smaller than the size of the nozzle that produce them. Furthermore, the EHD nano-inkjet can eject high viscosity liquid through the nozzle forming tiny structures. These unique features distinguish EHD printing from conventional methods for sub-micron resolution printing. In this presentation, I will introduce the recent research results regarding the EHD nano-inkjet and the printing system, which has been applied to solar cell or thin film transistor applications.

• Molecules and Cells
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• v.43 no.3
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• pp.298-303
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• 2020

Cryo-electron microscopy (cryo-EM) is now the first choice to determine the high-resolution structures of huge protein complexes. Grids with two-dimensional arrays of holes covered with a carbon film are typically used in cryo-EM. Although semi-automatic plungers are available, notable trial-and-error is still required to obtain a suitable grid specimen. Herein, we introduce a new method to obtain thin ice specimens using real-time measurement of the liquid amounts in cryo-EM grids. The grids for cryo-EM strongly diffracted laser light, and the diffraction intensity of each spot was measurable in real-time. The measured diffraction patterns represented the states of the liquid in the holes due to the curvature of the liquid around them. Using the diffraction patterns, the optimal time point for freezing the grids for cryo-EM was obtained in real-time. This development will help researchers rapidly determine high-resolution protein structures using the limited resource of cryo-EM instrument access.

• Applied Microscopy
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• v.39 no.4
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• pp.349-354
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• 2009

In this paper we have constructed three dimensional images and examined structural failure on thin film transistor (TFT) liquid crystal display (LCD) by using dual-beam focused ion beam (FIB) and IMOD software. Specimen was sectioned with dual-beam focused ion beam. Series of two dimensional images were obtained by scanning electron microscopy. Three dimensional reconstruction was constructed from them by using IMOD software. The short defect between Gate layer and Data layer was found from the result of three dimensional reconstruction. That phenomena made the function of the gate lost and data signal supplied to the electrode though the Drain continuously. That signal made continuous line defect. The result of the three dimensional reconstruction, serial section, SEM imaging by using the FIB will be the foundation of the next advanced study.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.307.2-307.2
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• 2016

In this study, we synthesized Au nanoparticles (AuNPs) in polyacrylonitrile (PAN) thin films using a simple annealing process in the solid phase. The synthetic conditions were systematically controlled and optimized by varying the concentration of the Au salt solution and the annealing temperature. X-ray photoelectron spectroscopy (XPS) confirmed their chemical state, and transmission electron microscopy (TEM) verified the successful synthesis, size, and density of AuNPs. Au nanoparticles were generated from the thermal decomposition of the Au salt and stabilized during the cyclization of the PAN matrix. For actual device applications, previous synthetic techniques have required the synthesis of AuNPs in a liquid phase and an additional process to form the thin film layer, such as spin-coating, dip-coating, Langmuir-Blodgett, or high vacuum deposition. In contrast, our one-step synthesis could produce gold nanoparticles from the Au salt contained in a solid matrix with an easy heat treatment. The PAN:AuNPs composite was used as the charge trap layer of an organic nano-floating gate memory (ONFGM). The memory devices exhibited a high on/off ratio (over $10^6$), large hysteresis windows (76.7 V), and a stable endurance performance (>3000 cycles), indicating that our stabilized PAN:AuNPs composite film is a potential charge trap medium for next generation organic nano-floating gate memory transistors.

• International Journal of Precision Engineering and Manufacturing
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• v.1 no.1
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• pp.98-105
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• 2000

The projectors using liquid crystal display(LCD) have faults such as low optical efficiency, low brightness and even heat generation. To solve these problems reflective-type spatial light modulators based on MEMS (Microelectromechanical Systems) technology have emerged. Digital Micromirror DeviceTM(DMDTM), which was already developed by Texas Instruments Inc., and Thin-film Micromirror ArrayTM(TMATM), which has been recently developed by Daewoo Electronics Co., are the representative examples. The display using TMATM has particularly much higher optical efficiency than other projectors. But the micromirrors manufactured by semiconductor processes have inevitable distortion because of the limitations of the manufacturing processes, so that the distortions of their surfaces have great influence on the optical efficiency of the projector. This study investigated the effects of mirror flatness on the optical performance, including the optical efficiency, of the TMATM projector. That is to say, as a part of the efforts to enhance the performance of the TMATM projector, how much influence the form errors of a micromirror surface exert on the optical efficiency and the modulation of gray scale of the projector were analyzed through a pertinent modeling and simulations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.403-406
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• 1999

The influence of temperature variation (25～125$^{\circ}C$) on poly-Si thin-film transistors (TFT's) was investigated by examining the electrical properties change of poly-Si films formed by solid phase crystallization (SPC). The n-channel poly-Si TFT's fabricated by SPC with channel length of 1.5 and loon ,respectively, exhibit good characteristics with a high ${\mu}$$\sub$FE/ ($\geq$82 and $\geq$60$\textrm{cm}^2$/V-s in 1.5 and 10$\mu\textrm{m}$, respectively), low V$\sub$t/, ($\leq$1.52 and $\leq$ 2.75V in 1.5 and 10$\mu\textrm{m}$, respectively), low S$\sub$t/, and good ON-OFF characteristics in spite of temperature variation. Thus, poly-Si films formed by SPC can be applied for the application to poly-Si TFT liquid crystal display with peripheral integrated circuits.

• Applied Science and Convergence Technology
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• v.24 no.3
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• pp.53-59
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• 2015

The field-effect transistors (FETs) with a graphene-based p-n junction channel were fabricated using the patterned self-assembled monolayers (SAMs). The self-assembled 3-aminopropyltriethoxysilane (APTES) monolayer deposited on $SiO_2$/Si substrate was patterned by hydrogen plasma using selective coating poly-methylmethacrylate (PMMA) as mask. The APTES-SAMS on the $SiO_2$ surface were patterned using selective coating of PMMA. The APTES-SAMs of the region uncovered with PMMA was removed by hydrogen plasma. The graphene synthesized by thermal chemical vapor deposition was transferred onto the patterned APTES-SAM/$SiO_2$ substrate. Both p-type and n-type graphene on the patterned SAM/$SiO_2$ substrate were fabricated. The graphene-based p-n junction was studied using Raman spectroscopy and X-ray photoelectron spectroscopy. To implement low voltage operation device, via ionic liquid ($BmimPF_6$) gate dielectric material, graphene-based p-n junction field effect transistors was fabricated, showing two significant separated Dirac points as a signature for formation of a p-n junction in the graphene channel.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.529-529
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• 2006

Several laboratories worldwide have demonstrated the feasibility of producing amorphous silicon thin film transistor (TFT) arrays at temperatures that are sufficiently low to be compatible with flexible foils such as stainless steel or high temperature polyester. These arrays can be used to fabricate flexible high information content display prototypes using a variety of different display technologies. However, several questions must be addressed before this technology can be used for the economic commercial production of displays. These include process optimization and scale-up to address intrinsic electrical instabilities exhibited by these kinds of transistor device, and the development of appropriate techniques for the handling of flexible substrate materials with large coefficients of thermal expansion. The Flexible Display Center at Arizona State University was established in 2004 as a collaboration among industry, a number of Universities, and US Government research laboratories to focus on these issues. The goal of the FDC is to investigate the manufacturing of flexible TFT technology in order to accelerate the commercialization of flexible displays. This presentation will give a brief outline of the FDC's organization and capabilities, and review the status of efforts to fabricate amorphous silicon TFT arrays on flexible foils using a low temperature process. Together with industrial partners, these arrays are being integrated with cholesteric liquid crystal panels, electrophoretic inks, or organic electroluminescent devices to make flexible display prototypes. In addition to an overview of device stability issues, the presentation will include a discussion of challenges peculiar to the use of flexible substrates. A technique has been developed for temporarily bonding flexible substrates to rigid carrier plates so that they may be processed using conventional flat panel display manufacturing equipment. In addition, custom photolithographic equipment has been developed which permits the dynamic compensation of substrate distortions which accumulate at various process steps.

• Journal of Information Display
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• v.10 no.1
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• pp.33-36
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• 2009

A new hybrid silicon thin-film transistor (TFT) fabrication process using the DPSS laser crystallization technique was developed in this study to realize low-temperature poly-Si (LTPS) and a-Si:H TFTs on the same substrate as a backplane of the active-matrix liquid crystal flat-panel display (AMLCD). LTPS TFTs were integrated into the peripheral area of the activematrix LCD panel for the gate driver circuit, and a-Si:H TFTs were used as a switching device of the pixel electrode in the active area. The technology was developed based on the current a-Si:H TFT fabrication process in the bottom-gate, back-channel etch-type configuration. The ion-doping and activation processes, which are required in the conventional LTPS technology, were thus not introduced, and the field effect mobility values of $4\sim5cm^2/V{\cdot}s$ and $0.5cm^2/V{\cdot}s$ for the LTPS and a-Si:H TFTs, respectively, were obtained. The application of this technology was demonstrated on the 14.1" WXGA+(1440$\times$900) AMLCD panel, and a smaller area, lower power consumption, higher reliability, and lower photosensitivity were realized in the gate driver circuit that was fabricated in this process compared with the a-Si:H TFT gate driver integration circuit