• Journal of Information Display
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• v.7 no.3
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• pp.1-4
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• 2006

2.22-inch qVGA $(240{\times}320)$ amorphous silicon thin film transistor liquid active matrix crystal display (a-Si TFT-AMLCD) panel has been successfully demonstrated employing a 2.5 um fine-patterning technology by a wet etch process. Higher resolution 2.22-inch qVGA LCD panel with an aperture ratio of 58% can be fabricated as the 2.5 um fine pattern formation technique is integrated with high thermal photo-resist (PR) development. In addition, a novel concept of unique a-Si TFT process architecture, which is advantageous in terms of reliability, was proposed in the fabrication of 2.22-inch qVGA LCD panel. Overall results show that the 2.5 um fine-patterning is a considerably significant technology to obtain higher aperture ratio for higher resolution a-Si TFT-LCD panel realization.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.4
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• pp.367-372
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• 2002

The vertically well-aligned carbon nanotubes(CNTs) were successfully grown on Ni coated silicon wafer substrate by DC bias-assisted PECVD(Plasma Enhanced Chemical Vapor Deposition). As a catalyst, Ni thin film of thickness ranging from 15~30nm was prepared by electron beam evaporator method. In order to find the optimum growth condition, the type of gas mixture such as $C_2H_2-NH_3$ was systematically investigated by adjusting the gas mixing ratio at $570^{\circ}C$ under 0.4Torr. The diameter of the grown CNTs was 40~200nm and the diameter of the CNTs increased with increasing the Ni particles size. TEM images clearly showed carbon nanotubes to be multiwalled. The measured turn-on field was $3.9V/\mu\textrm{m}$ and an emission current of $1.4{\times}10^4A/\textrm{cm}^2$ was $7V/\mu\textrm{m}$. The CNTs grown by bias-assisted PECVD was able to demonstrate high quality in terms of vertical alignment, crystallization of graphite and the processing technique at low temperature of $570^{\circ}C$ and this can be applied for the emitter tip of FEDs.

• Journal of the Korean Ceramic Society
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• v.44 no.7
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• pp.375-380
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• 2007

Tribological properties of carbon layers produced by high temperature chlorination of SiC ceramic and DLC (diamond-like carbon) coatings produced by ion plating method were investigated and compared. Carbon coatings were produced by exposure of ball and disc type SiC in chlorine and hydrogen gas mixtures at $1200^{\circ}C$. After treatment for 10 h, dense carbon films up to $180{\mu}m$ in thickness were formed. Tribological behavior of newly developed carbon films were compared with that of DLC films. Wear resistance and frictional coefficient of the surface modified ball and disc type SiC were significantly improved compared to an untreated SiC specimen, and also the modified carbon layer had better performance than DLC coatings. Therefore, in this study, the newly developed carbon films have several advantages over existing carbon coatings such as DLC coatings and showed superior tribological performances.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.533-536
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• 2001

Single crystal cubic silicon carbide(3C-SiC) thin film were deposited on Si(100) substrate up to a thickness of 4.3 $\mu\textrm{m}$ by APCVD(atmospheric pressure chemical vapor deposition) method using hexamethyildisilane(HMDS) at 1350$^{\circ}C$. The HMDS flow rate was 0.5 sccm and the carrier gas flow rate was 2.5 slm. The HMDS flow rate was important to get a mirror-like. The growth rate of the 3C-SiC films was 4.3 $\mu\textrm{m}$/hr. The 3C-SiC epitaxical layers on Si(100) were characterized by XRD(X-ray diffraction), raman scattering and RHEED(reflection high-energy electron diffraction), respectively The 3C-SiC distinct phonons of TO(transverse optical) near 796 cm$\^$-1/ and LO(longitudinal optical) near 974${\pm}$1 cm$\^$-1/ were recorded by raman scattering measurement. The deposition films were identified as the single crystal 3C-SiC phase by XRD spectra(2$\theta$=41.5$^{\circ}$). Also, with increase of films thickness, RHEED patterns gradually changed from a spot pattern to a streak pattern

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.377-377
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• 2007

A simplified integration process including packaging is presented, which enables the realization of the portable fluorescence detection system. A fluorescence detection microchip system consisting of an integrated PIN photodiode, an organic light emitting diode (OLED) as the light source, an interference filter, and a microchannel was developed. The on-chip fluorescence detector fabricated by poly(dimethylsiloxane) (PDMS)-based packaging had thin-film structure. A silicon-based integrated PIN photo diode combined with an optical filter removed the background noise, which was produced by an excitation source, on the same substrate. The active area of the finger-type PIN photo diode was extended to obtain a higher detection sensitivity of fluorescence. The sensitivity and the limit of detection (LOD S/N = 3) of the system were $0.198\;nA/{\mu}M$ and $10\;{\mu}M$, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.37-38
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• 2007

This paper reports the characteristics of piezoelectric microspeakers that are audible in open air with high quality piezoelectric AlN thin film according to the materials properties. When we use a tensile-stressed silicon nitride diaphragm as a supporting layer, the Sound Pressure Level (SPL) is relatively small. However, the SPL of the fabricated microspeakers that have compressive-stressed composite diaphragm show higher output pressure than those of tensile-stressed diaphragm. It produces more than 60dB from 100Hz to 15kHz and the highest SPL is about 100dB at 9.3kHz with 20 Vpeak-to-peak sinusoidal input biases and at 10 mm distances from the fabricated microspeakers to the reference microphone.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.1
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• pp.61-66
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• 2002

A method for designing antireflection (AR) and antistatic (AS) coating layer by the use of conducting polymer as an electrically conductive transparent layer is proposed. The conducting AR coating is composed of four-layer with alternating high and low refractive index layer: silicon dioxide (n=1.44) and titanium dioxide (n=2.02) prepared at low temperature by sol-gel method are used as the low and high refractive index layer, respectively. The poly(3,4-ethylenedioxythiophene) which has the surface resistivity of 10$^4$Ω/$\square$ is used as a conductive layer. Optical constant of each ARAS coating layers such as refractive index and optical thickness were measured by 7he spectroscopic ellipsometer and from the measured optical constants the spectral properties such as reflectance and transmittance were simulated in the risible region. The reflectance of ARAS films on glass substrate was below 1 %R and the transmittance was higher than 95 % in the visible wavelength (400-700 nm). The measured AR spectral properties was very similar to its simulated results.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.1-7
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• 2017

Multi-wafer planetary type chemical vapor deposition reactors are widely used in thin film growth and suitable for large scale production because of the high degree of growth rate uniformity and process reproducibility. In this study, a two-dimensional model for estimating the effect of the gap between satellite and wafer on the wafer surface temperature distribution is developed and analyzed using computational fluid dynamics technique. The simulation results are compared with the results obtained from an analytical method. The simulation results show that a drop in the temperature is noticed in the center of the wafer, the temperature difference between the center and wafer edges is about $5{\sim}7^{\circ}C$ for all different ranges of the gap, and the temperature of the wafer surface decreases when the size of the gap increases. The simulation results show a good agreement with the analytical ones which is based on one-dimensional heat conduction model.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• Journal of Sensor Science and Technology
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• v.10 no.3
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• pp.173-179
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• 2001

The currently used semiconductor pressure sensors are piezoresistive and capacitive type. Especially, semiconductor micro pressure sensors have a great deal of attention because of their small size. However, its fabrication processes are difficult, so that its yield is poor. For the purpose of resolving the drawbacks of the existing silicon pressure sensors, we demonstrate a new type of pressure sensor using PSFET(pressure sensitive field effect transistor) and investigate its operational characteristics. We used PZT(Pb(Zr,Ti)$O_3$) as a pressure sensing material. PZT thin films were deposited on a gate oxide of MOSFET by an rf-magnetron sputtering method. To abtain the stable phase, perovskite structure, furnace annealing technique have been employed in PbO ambient. The sensitivity of the PSFET was 0.38 mV/mmHg.