• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1333-1336
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• 1998

Hydrogenated amorphous silicon(a-Si:H) films which were deposited by plasma enhanced chemical deposition(PECVD) have been recrystallized by the two-step rapid thermal annealing(RTA) employing the halogen lamp. The a-Si:H films evolve hydrogen explosively during the high temperature crystallzation step. In result, the recrystallized polycrystalline silicon(poly-Si) films have poor surface morphology. In order to avoid the hydrogen evolution, the films have undergone the dehydrogenation step prior to the crystallization step Before the RTA process, the active area of thin film transistors (TFT's) was patterned. The prepatterning of the a-Si:H active islands may reduce thermal damage to the glass substrate during the recrystallization. The computer generated simulation shows the heat propagation from the a-Si:H islands into the glass substrate. We have fabricated the poly-Si TFT's on the silicon wafers. The maximun ON/OFF current ratio of the device was over $10^5$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.4
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• pp.285-289
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• 2009

Small RFID tag antenna were fabricated on Si substrate and their physical and electrical properties were evaluated. With decreasing the size of tag antenna on Si substrate, small SMD-type RFID tags could be fabricated, which is very useful for various applications including PCB tracking. Firstly, electromagnetic properties on tag antenna pattern were simulated with HFSS. The setup frequency was 13.56 MHz of HF-band RFID. The line-width and line-gap were modeled in the range of $50{\sim}200{\mu}m$. S parameters, SRF, and Q value were calculated from the model. When the line-width and line-gap were 100 urn and the loop-turn was 10, the SRF was 80 MHz and the Q value was ca. 9. When the microstrip antenna pattern of aluminum was fabricated by using DC sputtering, Vpp of ca. 1.6 V was obtained when the reader-tag distance was 40 mm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.10
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• pp.620-624
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• 2016

Ferroelectric $Pb(Zr_{0.52}Ti_{0.48})O_3$ (PZT) films were deposited on SrTiO3(100) substrate by using conductive $SrRuO_3$ films as underlayer and their structural and ferroelectric properties were investigated. PZT films were grown in (00l) orientation on well lattice-matched pseudo-cubic $SrRuO_3$ films. Thickness dependence of ferroelectric and electrical properties of PZT films was investigated. PZT film with 400 nm thickness showed a remanent polarization ($P_r$) of $29.0{\mu}C/cm^2$ and coercive field ($E_c$) of 83 kV/cm, and $P_r$ decreased and $E_c$ increased with thickness reduction. The dielectric constant for PZT films showed gradual decrease with thickness reduction. Breakdown field of PZT films did not show the thickness dependence and displayed as high value as 1 MV/cm.

• Transactions on Electrical and Electronic Materials
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• v.18 no.5
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• pp.253-256
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• 2017

A thin Te interlayer was applied to a Ni/n-InGaAs contact to reduce the contact resistance between Ni-InGaAs and n-InGaAs. A 5-nm-thick Te layer was first deposited on a Si-doped n-type $In_{0.53}Ga_{0.47}As$ layer, followed by in situ deposition of a 30-nm-thick Ni film. After the formation of the Ni-InGaAs alloy by rapid thermal annealing at $300^{\circ}C$ for 30 s, the extracted specific contact resistivity (${\rho}_c$) reduced by more than one order of magnitude from $2.86{\times}10^{-4}{\Omega}{\cdot}cm^2$ to $8.98{\times}10^{-6}{\Omega}{\cdot}cm^2$ than that of the reference sample. A thinner Ni-InGaAs alloy layer with a better morphology was obtained by the introduction of the Te layer. The improved interface morphology and the graded Ni-InGaAs layer formed at the interface were believed to be responsible for ${\rho}_c$ reduction.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.6
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• pp.817-820
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• 2012

We studied p-type capacitance characteristics of ZnO thin-film transistors (TFT's), grown by metal organic chemical vapor deposition (MOCVD). We compared two ZnO TFT's: one grown at $450^{\circ}C$ and the other grown at $350^{\circ}C$. ZnO grown at $450^{\circ}C$ showed smooth capacitance profile with electron density of $1.5{\times}10^{20}cm^{-3}$. In contrast, ZnO grown at $350^{\circ}C$ showed a capacitance jump when gate voltage was changed to negative voltages. Current-voltage characteristics measured in the two samples did not show much difference. We explain that the capacitance jump is related to p-type ZnO layer formed at the $SiO_2$ interface. Current-voltage and capacitance-voltage data support that p-type characteristics are observed only when background electron density is very low.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.211.2-211.2
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• 2014

Epitaxial complex oxide thin film heterostructures have attracted a great attention for their multifunctional properties, such as ferroelectricity, and ferromagnetism. Two dimensional electron gas (2DEG) confined at the interface between two insulating perovskite oxides such as LaAlO3/SrTiO3 interface, provides opportunities to expand various electronic and memory devices in nano-scale. Recently, it was reported that the conductivity of 2DEG could be controlled by external electric field. However, the switched conductivity of 2DEG was not stable with time, resulting in relaxation due to the reaction between charged surface on LaAlO3 layer and atmospheric conditions. In this report, we demonstrated a way to control the conductivity of 2DEG in non-volatile way integrating ferroelectric materials into LAO/STO heterostructure. We fabricated epitaxial Pb(Zr0.2Ti0.8)O3 films on LAO/STO heterostructure by pulsed laser deposition. The conductivity of 2DEG was reproducibly controlled with 3-order magnitude by switching the spontaneous polarization of PZT layer. The controlled conductivity was stable with time without relaxation over 60 hours. This is also consistent with robust polarization state of PZT layer confirmed by piezoresponse force microscopy. This work demonstrates a model system to combine ferroelectric material and 2DEG, which guides a way to realize novel multifunctional electronic devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.351.1-351.1
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• 2014

In this study, we prepared the solution-based In-Ga-Zn oxide thin film transistors (IGZO TFTs) of multistacked active layer and characterized the gate bias instability by measuring the change in threshold voltage caused by stacking. The solutions for IGZO active layer were prepared by In:Zn=1:1 mole ratio and the ratio of Ga was changed from 20% to 30%. The TFTs with multistacked active layer was fabricated by stacking single, double and triple layers from the prepared solutions. As the number of active layer increases, the saturation mobility shows the value of 1.2, 0.8 and 0.6 (). The electrical properties have the tendency such as decreasing. However when gate bias VG=10 V is forced to gate electrode for 3000 s, the threshold voltage shift was decreased from 4.74 V to 1.27 V. Because the interface is formed between the each layers and this affected the current path to reduce the electrical performances. But the uniformity of active layer was improved by stacking active layer with filling the hole formed during pre-baking so the stability of device was improved. These results suggest that the deposition of multistacked active layer improve the stability of the device.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.330.1-330.1
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• 2014

개인용 노트북, 태블릿 PC, 핸드폰 기술 발전에 의해 언제 어디서나 데이터를 작성하고 기록하는 일들이 가능해졌다. 특히 cloud 시스템을 이용하여 데이터를 휴대기기에 직접 저장하지 않고 server에 기록하는 일들이 가능해짐에 따라 server 기기의 성능, server-room power 및 space 에 대한 관심이 증가하였다. Storage class memory (SCM) 이란 memory device와 storage device의 장점을 결합한 memory를 일컫는 기술로 현재 소형 디바이스 부분부터 점차 그 영역을 넓히고 있다. 그중 phase change material을 이용한 phase change memory (PCM) 기술이 가장 각광받고 있다. PCM의 경우 scaling됨에 의해 cell간의 열 간섭으로 인한 data 손실의 우려가 있어 cell의 면적을 최소화 하여 소자를 제작하여야 한다. 기존의 sputtering등의 PVD 방법으로는 한계가 있어 ALD 공정을 이용한 PCM에 대한 연구가 활발히 진행중이다. 특히 tellurium 원료기체로 silyl 화합물 [1]을 사용하여 주로 $Ge_2Sb_2Te_5$의 조성에 초점을 맞춰 진행되고 있으나, 세부 공정에 대한 기본적인 연구는 미비하다. 본 연구에서는 Ge-Sb-Te 3원계 박막을 형성하기 위한 Sb-Te 화합물의 증착 공정에 대한 연구를 수행하였다. 특히 원료기체로 Si이 없는 새로운 Te 원료기체를 이용하여 조성 조절을 하였고, 박막의 물성을 분석하였다. 또한 공정온도에 따른 박막의 물성 변화를 분석하였다.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.56-58
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• 2006

본 논문은 PVD(Physical Vapor Deposition)의 마그네트론 스퍼터(Magnetron sputter) 박막코팅(Thin film coating) 공정에서 플라즈마(Plasma)를 발생시키고 제어하는 DC 전원공급 장치에 관한 것이다. 이 논문에서는 임피던스의 변화가 심하고 아크(Arc)가 빈번히 발생하는 플라즈마 부하의 특성에 대해, 과도상태(Transient state)의 출력제어 성능을 향상시키고 아크 발생 시 부하로 전가되는 아크에너지를 저감시키기 위한 직류 전원 공급 장치에 대해 소개한다. 전원장치는 수하특성을 가지며 플라즈마 부하에 적합한 출력 제어성을 확보하고 아크 에너지를 최소화하기 위해 고주파 L-C 직렬공진회로 기법을 적용한다. 개발된 DC 20kW급 전원 장치는 인버터와 고주파 절연변압기, 정류기로 구성된다. 인버터는 $100{\sim}200kHz$의 제어주파수로 PFM 및 PWM 제어를 하며, 단위용량 5kW급 컨버터 4개를 직, 병렬 연결하여 출력리플을 최소화 하였다. 개발된 장치의 우수한 제어성능은 실제 플라즈마 공정에서 시험 평가한 결과를 통해 검증할 수 있었다.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.873-875
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• 1999

We have fabricated good quality superconducting $YBa_{2}Cu_{3}O_{7-\delta}$ thin films on Hastelloy(Ni-Cr-Mo alloys) metallic substrate with $CeO_2$ and $BaTiO_3$ buffer layers in-situ by pulsed laser deposition in a multi-target processing chamber. We have chosen $CeO_2$ as a buffer layer which has cubic structure of $5.41{\AA}$ lattice parameter and only 0.2% of lattice mismatch with YBCO. $CeO_2$ layer may be helpful for power transmission due to its conducting property. In order to enhance the crystallization of YBCO films on metallic substrates. we deposited $CeO_2$ and $BaTiO_3$ buffer layers at various temperatures. The YBCO superconducting tape fabricated with $BaTiO_3$ and $CeO_2$ buffer layers shows 85K of transition temperature and about $8.4{\times}10^4A/cm^2$ of critical current density at 77K.