• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.422-448
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• 1996

Low-temperature epitaxial growth of Si and SiGe layers of Si is one of the important processes for the fabrication of the high-speed Si-based heterostructure devices such as heterojunction bipolar transistors. Low-temperature growth ensures the abrupt compositional and doping concentration profiles for future novel devices. Especially in SiGe epitaxy, low-temperature growth is a prerequisite for two-dimensional growth mode for the growth of thin, uniform layers. UHV-ECRCVD is a new growth technique for Si and SiGe epilayers and it is possible to grow epilayers at even lower temperatures than conventional CVD's. SiH and GeH and dopant gases are dissociated by an ECR plasma in an ultrahigh vacuum growth chamber. In situ hydrogen plasma cleaning of the Si native oxide before the epitaxial growth is successfully developed in UHV-ECRCVD. Structural quality of the epilayers are examined by reflection high energy electron diffraction, transmission electron microscopy, Nomarski microscope and atomic force microscope. Device-quality Si and SiGe epilayers are successfully grown at temperatures lower than 600℃ after proper optimization of process parameters such as temperature, total pressure, partial pressures of input gases, plasma power, and substrate dc bias. Dopant incorporation and activation for B in Si and SiGe are studied by secondary ion mass spectrometry and spreading resistance profilometry. Silicon p-n homojunction diodes are fabricated from in situ doped Si layers. I-V characteristics of the diodes shows that the ideality factor is 1.2, implying that the low-temperature silicon epilayers grown by UHV-ECRCVD is truly of device-quality.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.2
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• pp.263-274
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• 1996

Titanium dioxide ($TiO_{2}$) film has been widely used as anti-reflection coating for solar cells but not as masking oxide for metallisation and diffusion of impurities. In this paper we have investigated the properties of $TiO_{2}$ for possible incorporation into solar cell processing sequence. Thus the use of a spray deposition system to form the $TiO_{2}$ film and the characterisation of this film to ascertain its suitability to solar cell processing. The spray-on $TiO_{2}$ film was found to be resistant to all the chemicals used in conjunction with solar cell processing. The high temperature anealing (in oxygen ambient) of the spray-on $TiO_{2}$ film resulted in an increased refractive index, which indicated the growth of an underlying thin film of $SiO_{2}$ film for the passivation of silicon surface which would reduce the recombination activities of the fabricated device. Most importantly, the successful incorporation of the $TiO{2}$ film will lead to the reduction of the many high temperature processing steps of solar cell to only one.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.5
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• pp.374-378
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• 2010

The effects of $O_2$ plasma pretreatment on the properties of Ga-doped ZnO films on polyimide substrate were studied. GZO films were fabricated by RF magnetron sputtering process. To improve surface energy and adhesion between the polyimide substrate and the GZO film, $O_2$ plasma pretreatment process was used prior to GZO sputtering. As the RF power and the treatment time increased, the crystallinity increased and the contact angle decreased significantly. When the RF power was 100 W and the treatment time was 120 sec, the resistivity of GZO films on the polyimide substrate was $1.90{\times}10^{-3}{\Omega}-cm$.

• Journal of Electrochemical Science and Technology
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• v.8 no.3
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• pp.250-256
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• 2017

A graphene electrode with a novel in-plane structure is proposed and successfully adopted for use in supercapacitor applications. The in-plane structure allows electrolyte ions to interact with all the graphene layers in the electrode, thereby maximizing the utilization of the electrochemical surface area. This novel structure contrasts with the conventional out-of-plane stacked structure of such supercapacitors. We herein compare the volumetric capacitances of in-plane- and out-of-plane-structured devices with reduced multi-layer graphene oxide films as electrodes. The in-plane-structured device exhibits a capacitance 2.5 times higher (i.e., $327F\;cm^{-3}$) than that of the out-of-plane-structured device, in addition to an energy density of $11.4mWh\;cm^{-3}$, which is higher than that of lithium-ion thin-film batteries and is the highest among in-plane-structured ultra-small graphene-based supercapacitors reported to date. Therefore, this study demonstrates the potential of in-plane-structured supercapacitors with high volumetric performances as ultra-small energy storage devices.

• Applied Chemistry for Engineering
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• v.26 no.6
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• pp.725-729
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• 2015

Organic light emitting diodes (OLEDs) are regarded as the next generation display and solid-state lighting due to their superb achievements from extensive research efforts on improving the efficiency and stability of OLEDs in addition to developing new materials. Herein, efficient green phosphorescent OLEDs were obtained by using hexaazatrinaphthylene (HAT) derivatives as a hole injection layer. External quantum and current efficiencies of OLEDs were enhanced from 8.8% and 30.8 cd/A to 13.6% and 47.7 cd/A, respectively by inserting a thin layer of HAT derivatives between the ITO and hole transporting layer. The enhancement of OLEDs was found to be originated from the inserted HAT derivatives, which resulted in the optimized hole-electron balance inside the emission layer.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.279-283
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• 2012

In is paper, we design and implement the low power, high speed touch screen controller that calculates and outputs the coordinate of touch point on the touch screen of mobile devices. The system clock is 10HMz, the number of input channels is 21, standby current is $20{\mu}A$, dynamic range of input is 140pF~400pF and the response time is 0.1ms/frame. It contains the power management unit for low power, automatic impedance calibration unit in order to adapt to humidity, temperature and evaluation board, adjacent key and pattern interference suppression unit, serial interface unit of I2C and SPI. The function and performance is verified by using FPGA and $0.18{\mu}m$ CMOS standard process. The implemented touch screen is designed for using in the double layer ITO(Indium Thin Oxide) module with diamond pattern and single layer ITO module for cost-effective which are applied to mobile phone or smart remote controller.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.89-100
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• 1997

This paper investigated a new type of low voltage threshold switch (LVTS). As distinguished from the many other types of electronic threshold switches, the LvTS is ; voltage controlled, occurs at low voltages ($V_{2}$ $O_{5}$lV devices. The average low threshold voltage < $V_{LVT}$>=218 mV (standard deviation =24mV~kT/q, where T=300K), and was independent of the device area (x100) and amorphous oxide occurred in an ~22.angs. thick interphase of the V/amorphous- $V_{2}$ $O_{5}$ contacts. At $V_{LVT}$ there was a transition from an initially low conductance (OFF) state into a succession of quantized states of higher conductance (ON). The OFF state was spatically homogeneous and dominated by tunneling into the interphase. The ON state conductances were consistent with the quantized conductances of ballistic transport through a one dimensional, quantum point contact. The temeprature dependence of $V_{LVT}$, and fit of the material parameters (dielectric function, barrier energy, conductivity) to the data, showed that transport in the OFF and ON states occurred in an interphase with the characteristics of, respectively, semiconducting and metallic V $O_{2}$. The experimental results suggest that the LVTS is likely to be observed in interphases produced by a critical event associated with an inelastic transfer of energy.rgy.y.rgy.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.155-162
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• 1997

Zinc oxide(ZnO) thin films were deposited on r-plane sapphires from a solution containing zinc acetate. The films were obtained in a hot wall reactor by the pyrolysis of an aerosol produced by an ultrasonic generator. The crystallinity, surface morphology and composition of the films have been studied using the x-ray diffraction method(XRD) scanning electron microscopy(SEM) and Auger electron spectroscopy (AES) respectively. The influences of the substrate temperature on the crystallinity of the films were studied. Strongly (110) oriented ZnO films were obtained at a substrate temperature of $350^{\circ}C$. The resistivity was increased to above $3{\times}10^{6}{\Omega}{\cdot}cm$ with copper doping and vapor oxidation.

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.306-308
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• 2007

Poly(ethylene glycol) dimethyl ether (PEGDME)/fumed silica/ 1-methyl -3-propylimidazolium iodide (MPII)/$I_2$ mixtures were used as polymer electrolytes in solid state dye-sensitized solar cells (DSSCs). The contents of MPII were changed and the concentration of $I_2$ was fixed at 0.1 mole% with respect to the MPII. The maximum ionic conductivity was obtained at [EG]:[MPII]:[$I_2$]=10:1.5:0.15. It was supposed that the maximum of ionic conductivities would match with that of cell efficiencies, if the ionic conductivity is a rate determining step in the sol id state DSSCs. However, the maximum composition did not show the maximum solar cell performance, indicating the mismatch between ionic conductivity and cell performance. This suggests that the ionic conductivity may not be the rate controlling step in determining the cell efficiency in these experimental conditions, whereas other parameters such as the electron recombination might play an important role. Thus, we tried to modify the surface of the $TiO_2$ particles by coating a thin metal oxide such as $Al_2O_3$ or $Nb_2O_5$ layer to prevent electron recombination. As a result, the maximum of the cell efficiency was shifted to that of the ionic conductivity. The peak shifts were also attempted to be explained by the diffusion coefficient and the lifetime of electrons in the $TiO_2$ layer.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.66-66
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• 1999

최근 들어 다결정 SiGe은 MOS(Metal-Oxide-Semiconductor)에서 기존에 사용되던 다결정 Si 공정과의 호환성 및 여러 장점으로 인하여 다결정 Si 대안으로 많은 연구가 진행되고 있다. 고농도로 도핑된 P type의 다결정 SiGe은 Ge의 함량에 따른 일함수의 조절과 낮은 비저항으로 submicrometer CMOS 공정에서 게이트 전극으로 이용하려는 연구가 진행되고 있으며, 55$0^{\circ}C$ 이하의 낮은 온도에서도 증착이 가능하고, 도펀트의 활성화도가 높아서 TFT(Thin Film Transistor)에서도 유용한 재료로 검토되고 있다. 현재까지 다결정 SiGe의 증착은 MBE, APCVD, RECVD. HV/LPCVD 등 다양한 방법으로 이루어지고 있다. 이중 HV/LPCVD 방법을 이용한 증착은 반도체 공정에서 게이트 전극, 유전체, 금속화 공정 등 다양한 공정에서 사용되고 있는 방법으로 현재 사용되고 있는 반도체 공정과의 호환성의 장점으로 다결정 SiGe 게이트 전극의 증착 공정에 적합하다고 할 수 있다. 본 연구에서는 HV/LPCVD 방법을 이용하여 게이트 전극으로의 활용을 위한 다결정 SiGe의 증착 메카니즘을 분석하고 Ex-situ implantation 후 열처리에 따라 나타나는 활성화 정도를 분석하였다. 도펀트를 첨가하지 않은 다결정 SiGe을 주성엔지니어링의 EUREKA 2000 장비를 이용하여, 1000$\AA$의 열산화막이 덮혀있는 8 in 웨이퍼에 증착하였다. 증착 온도는 55$0^{\circ}C$에서 6$25^{\circ}C$까지 변화를 주었으며, 증착압력은 1mtorr-4mtorr로 유지하였다. 낮은 증착압력으로 인한 증착속도의 감소를 방지하기 위하여 Si source로서 Si2H6를 사용하였으며, Ge의 Source는 수소로 희석된 10% GeH4와 100% GeH4를 사용하였다. 증착된 다결정 SiGe의 Ge 함량은 RBS, XPS로 분석하였으며, 증착된 박막의 두께는 Nanospec과 SEM으로 관찰하였다. 또한 Ge 함량 변화에 따른 morphology 관찰과 변화 관찰을 위하여 AFM, SEM, XRD를 이용하였으며, 이온주입후 열처리 온도에 따른 활성화 정도의 관찰을 위하여 4-point probe와 Hall measurement를 이용하였다. 증착된 다결정 SiGe의 두게를 nanospec과 SEM으로 분석한 결과 Gem이 함량이 적을 때는 높은 온도에서의 증착이 더 빠른 증착속도를 나타내었지만, Ge의 함량이 30% 되었을 때는 온도에 관계없이 일정한 것으로 나타났다. XRD 분석을 한 결과 Peak의 위치가 순수한 Si과 순수한 Ge 사이에 존재하는 것으로 나타났으며, ge 함량이 많아짐에 따라 순수한 Ge쪽으로 옮겨가는 경향을 보였다. SEM, ASFM으로 증착한 다결정 SiGe의 morphology 관찰결과 Ge 함량이 높은 박막의 입계가 다결정 Si의 입계에 비해 훨씬 큰 것으로 나타났으며 근 값도 증가하는 것으로 나타났다.