• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.343-343
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• 2011

저온에서의 Thin Film Transistor (TFT) 혹은 Nonvolatile memory (NVM) 등의 MOS 구조 소자들의 높은 전기적 특성에 관한 연구들이 진행 되면서 mobility와 stability 그리고 구조화의 용이성에 대한 연구가 진행됨에 따라 amorphous silicon의 결정화를 통해 전기적 특성을 향상 시킨 Nanocrystalline silicon (nc-Si)/Microcrystalline silicon (${\mu}c$-Si)에 대한 연구가 관심을 받고 있다. 본 논문에서는 ${\leq}300^{\circ}C$에서 Inductively coupled plasma chemical vapor deposition를 이용한 TFT을 제작하였다. 가스비, 온도, 두께에 따른 결정화 정도를 Raman spectra를 통해 확인한 후 Bottom gate와 Top gate 구조의 TFT를 제작 하고 결정화에 따른 전기적 특성 향상과 그의 덧붙여 플라즈마 처리를 통한 특성 향상을 확인 하였다.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• Electrical & Electronic Materials
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• v.9 no.10
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• pp.1008-1012
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• 1996

I-V, C-V characteristics of inverted staggered type hydrogenerated amorphous silicon thin film transistor(a-Si:H TFT) was studied and experimentally verified. The results show that the log-log plot of drain current increased by voltage increase. The saturated drain current of DC output characteristics increased at a fixed gate voltage. According to the increase of gate voltage, activation energy of electron and the increasing width of Id at high voltage were decreased. Id saturation current saturated at high Vd over 4.5V, Vg-ld hysteresis characteristic curves occurred between -15V and 15V of Vg. Hysteresis current decreased at low voltage of -15V and increased at high voltage of 15V.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.57-62
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• 1999

Polycrystaline thin film transistors are fabricated on the transparent glass substrate by a lamp-scan annealing. The line-shaped lamp scanning method, which is profitable for large area process, effectively radiated silicon film on glass substrate. Amorphous silion film absorbs the light which is emitted from halogen-lamp and it transformed into crystalline silicon by metal-induced lateral crystallization. In order to enhance the annealing effect, capping layer was deposited on the whole substrate. When the scan speed was 1-2mm/sec, lateral crystallization of amorphous silicon under capping layer was 18~27${\mu}m/scan$. The thin film transistor fabricated by this method shows high electron mobility over 130$cm^2/V{\cdot}sec$

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.6
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• pp.229-235
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• 2002

This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.

• Journal of KIISE:Software and Applications
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• v.34 no.5
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• pp.447-454
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• 2007

TFT-LCD(Thin Film transistor liquid crystal display) has become actively used front panel display technology with increasing market. Intrinsically there is region of non uniformity with low contrast that to human eye is perceived as defect. As the gray level difference between the defect and the background is hardly distinguishable, conventional thresholding and edge detection techniques cannot be applied to detect the defect. Between the patterned and un-patterned LCD defects, this paper deals with un-patterned LCD defects by using independent component analysis, adaptive thresholding and skewness. Our method showed strong results even on noised LCD images and worked successfully on the manufacturing line.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.543-545
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• 2009

With injection-type source delivery system of atomic layer deposition (ALD), bottom-contact and bottom-gate thin-film transistors (TFTs) were fabricated with a poly-4-vinyphenol polymeric dielectric for the first time. The properties of the ZnO TFT were greatly influenced by the device structure and the process conditions. The zinc oxide TFTs exhibited a channel mobility of 0.43 $cm^2$/Vs, a threshold voltage of 0.85 V, a subthreshold slope of 3.30 V/dec, and an on-to-off current ratio of above $10^6$ with solid saturation.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.597-600
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• 2006

The silver gate and source/drain electrodes for an a-Si thin film transistor were fabricated by the selective electroless plating (SELP) process. Relevant physical properties including taper angle, uniformity and resistivity are investigated. The Ag layer was about 150nm to 250nm thick, the resistivity less than $3{\times}10^{-6}$ Ohm-cm and the taper angle 45'-60' and the nonuniformity less than 10% on G2 substrates. The transfer characteristics with the Ag gate, and source/drain electrodes respectively possessed good field effect mobility similar to conventionally fabricated a-Si TFTs. This process provided low resistivity, low cost and ease of processing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.395-395
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• 2007

We report on the fabrication of soluble pentacene-based thin-film transistors (TFTs) that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (SID) electrodes, gate dielectric, and gate electrode, respectively. The $NiO_x$ SID electrodes of which the work function is well matched to that of soluble pentacene are deposited on a soluble pentacenechannel by sputter deposited of NiO powder and show a moderately low but still effective transmittance of ~65% in the visible range along with a good sheet resistance of ${\sim}40{\Omega}/{\square}$. The maximum saturation current of our soluble pentacene-based TFT is about $15{\mu}A$ at a gate bias of -40showing a high field effect mobility of $0.06cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^4$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality soluble pentacene-based TFT.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.161-165
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• 2023

This paper designed a voltage feedback driving circuit to compensate for the characteristic deviation of the Active Matrix Organic Light Emitting Diode driving Thin Film Transistor. This paper describes a stable and fast circuit by applying charge sharing and polar stabilization methods. A 12-inch Organic Light Emitting Diode with a Double Wide Ultra eXtended Graphics Array resolution creates a screen distortion problem for line parasitism, and charge sharing and polar stabilization structures were applied to solve the problem. By applying Charge Sharing, all data lines are shorted at the same time and quickly positioned as the average voltage to advance the compensated change time of the gate voltage in the next operation period. A buffer circuit and a current pass circuit were added to lower the Amplifier resistance connected to the line as a polar stabilization method. The advantage of suppressing the Ringing of the driving Thin Film Transistor can be obtained by increasing the stability. As a result, a circuit was designed to supply a stable current to the Organic Light Emitting Diode even if the characteristic deviation of the driving Thin Film Transistor occurs.