• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.344-344
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• 2010

A capacitor with engineered tunnel barrier composed of High-k materials has been fabricated. Variable oxide thickness (VARIOT) barrier consisting of thin SiO2/HfO2/Al2O3 (2/1/3 nm) dielectric layers were used as engineered tunneling barrier. We studied the electrical characteristics of multi stacked tunnel layers for various RTA (Rapid Thermal Anneal) and FGA (Forming Gas Anneal) temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 춘계학술대회 논문집
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• pp.217-221
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• 1997

We have investigated the ferroelectric properties of multi-layered SrBi$_2$Ta$_2$$O_{9}$Pb(Zr,Ti)O$_3$, SBT/PZT, thin film capacitors. Specimens were prepared onto Pt-coated Si wafer by sol-gel method. Ferroelectric properties of these finns could be obtained only for thin SBT layers below 50nm in thickness. The values of dielectric constant and remnant polarization depend mainly on the thickness of SBT layer, which arises from the paraelectric interface layer between SBT and PZT due to the thermal diffusion of Pb. The value of remnant poarization of PZT/SBT is greater than that of SBT, and the plarization fatigue behaviors of PZT/SBT/Pt capacitors are somewhat improved as compared with those of PZT/Pt.t.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.100-101
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• 2007

Polymer thick film capacitors were successfully fabricated by using ink-jet printing and screen printing technology. First, a bottom electrode was patterned by ink-jet printing of a nano-sized silver ink. Next, a dielectric layer was formed by the screen printing, then a top electrode was pattern by ink-jet printing of a nano-sized silver ink. The printed area of the dielectric layers were changed into $2{\times}2m^2$and $4{\times}2m^2$, and also the area of the electrodes were patterned with $1{\times}1mm^2$ and $1{\times}3mm^2$. The thickness of the printed dielectric layer was ranged from 1.1 to $1.4{\mu}m$. The analysis of capacitances verified that the capacitances was proportional to the area of the printed electrode. The capacitances of the fabricated capacitors resulted in one third of the calculated capacitances.

• 전기학회논문지
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• 제56권1호
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• pp.117-122
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• 2007

LB method is one of the most interesting technique to arrange certain molecular groups at precise position relative to others. Also, the LB deposition technique can fabricate extremely thin organic films with a high degree of control over their thickness and molecular architecture. In this way, new thin film materials can be built up at the molecular level, and the relationship between these artificial structures and the properties of materials can be explored. In this paper, evaluation of physical properties was made for dielectric relaxation phenomena by the detection of the surface pressures and displacements current on the monolayer films of phospolipid monomolecular DLPC. Lipid thin films were manufacture by detecting deposition for the accumulation and the current was measured after the electric bias was applied across the manufactured MIM device. It is found that the phospolipid monolayer of dielectric relaxation takes a little time and depend on the molecular area. When electric bias is applied across the manufactured MIM device by the deposition condition of phospolipid mono-layer, it wasn't breakdown when the higher electric field to impress by increase of deposition layers.

• 한국항행학회논문지
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• 제16권4호
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• pp.635-640
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• 2012

본 논문에서는 접지된 2개의 유전체층 위의 도체띠 격자구조에 의한 TE (Transverse Electric) 산란문제를 도체경계조건과 수치해석 방법인 FGMM (Fourier-Galerkin Moment Method)를 적용하여 해석하였으며, 이 때 유도되는 표면전류밀도는 미지의 계수와 단순한 함수인 지수함수의 곱의 급수로 전개하였다. 전반적으로, 제안된 구조에서 영역-2의 유전체층의 비유전율 ${\epsilon}_{r2}$과 유전체 층의 두께 $t_2$가 증가함에 따라 반사전력이 증가하였다. 반사전력의 급변점들은 공진효과에 기인한 것으로 과거에 wood's anomaly라고 불리워졌으며, 수치계산 결과들은 기존 논문의 결과들과 일치하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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• pp.194-196
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• 2004

$BaTiO_3/SrTiO_3$ heterolayered thick films on the $Al_2O_3$ substrate by screen printing method with stacking periodicity. The stacking periodicity of $BaTiO_3/SrTiO_3$ heterolayer structure was varied from $(BaTi_O_3)_1/(SrTiO_3)_1$ to $(BaTi_O_3)_3/(SrTiO_3)_3$. The total thickness of the $BaTiO_3/SrTiO_3$ films was about $120{\mu}m$. There was an interdiffusion at the interface of the $BaTiO_3$ and $SrTiO_3$ layers. The dielectric constant of $BaTiO_3/SrTiO_3$ heterolayered thick films was increased with decreasing stacking periodicity of the $BaTiO_3/SrTiO_3$. The dielectric constant of the ($(BaTi_O_3)_1/(SrTiO_3)_1$ herterolayered thick films was about 1780.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.74-77
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• 2004

[ $HfO_2$ ] dielectric layers were grown on the p-type Si(100) substrate by metalorganic molecular beam epitaxy(MOMBE). Hafnium $t-butoxide[Hf(O{\cdot}t-C_4H_9)_4]$ was used as a Hf precursor and Argon gas was used as a carrier gas. The thickness of the layers was measured by scanning electron microscopy (SEM) and high-resolution transmission electron measurement(HR-TEM). The properties of the $HfO_2$ layers were evaluated by X-ray diffraction(XRD), high frequency capacitance-voltage measurement(HF C-V), current-voltage measurement(I-V), and atomic force measurement(AFM). HF C-V measurements have shown that $HfO_2$ layer grown by MOMBE has a high dielectric constant(k=19-21). The properties of $HfO_2$ films are affected by various process variables such as substrate temperature, bubbler temperature, Ar, and $O_2$ gas flows. In this paper, we examined the relationship between the $O_2/Ar$ gas ratio and the electrical properties of $HfO_2$.

• 대한금속재료학회지
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• 제48권3호
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• pp.256-261
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• 2010

In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.

• 한국인터넷방송통신학회논문지
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• 제21권1호
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• pp.49-54
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• 2021

본 논문에서는 2중 유전체층 사이의 저항띠 격자구조에 의한 E-분극 전자파 산란 문제는 전자파 수치해석방법으로 알려진 PMM(Point Matching method)를 이용하여 해석하였다. 경계조건들은 미지의 계수를 구하기 위하여 이용하였고, 저항띠의 해석을 위해 저항띠 경계조건을 적용하였다. 2중 유전층 사이의 비유전율과 두께 및 저항띠의 저항율에 대해 정규화된 반사전력과 투과전력을 계산하였다. 전반적으로 저항띠의 저항율이 작아지거나 유전체 층의 비유전율이 증가할수록 반사전력은 증가하였으며, 반사전력이 증가하면 투과전력은 상대적으로 감소하였다. 특히, 2중 유전체 층의 비유전율이 증가할수록 반사전력의 변곡점의 최소 값은 격자주기가 작아지는 방향으로 이동하였다. 본 논문의 제안된 구조에 대한 수치결과들은 기존논문의 수치해석 결과들과 비교하여 매우 잘 일치하였다.

• 한국인터넷방송통신학회논문지
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• 제19권2호
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• pp.47-52
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• 2019

본 논문에서는 2중 유전체층 사이의 완전도체띠 격자구조에 의한 TE(transverse electric) 산란 문제는 전자파 수치해석 방법으로 알려진 FGMM(Fourier-Galerkin moment method)를 이용하여 해석하였다. 경계조건들은 미지의 계수를 구하기 위하여 이용하였고, 도체띠의 해석을 위해 완전도체 경계조건을 적용하였다. 도체띠의 폭과 주기, 2중 유전층 사이의 비유전율과 두께 및 입사각에 대해 정규화된 반사전력과 투과전력을 계산하였다. 전반적으로 유전율의 값이 증가하면 반사전력은 증가하며, 상대적으로 투과전력은 감소하였다. 유전율이 증가할수록 도체띠에 유도되는 전류밀도는 양쪽 끝으로 진행하면서 증가하였다. 본 논문의 제안된 구조에 대한 수치결과들은 기존 논문의 수치해석 결과들과 비교하여 매우 잘 일치하였다.