• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.98-106
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• 1994

To realize high accuracy and high speed we developed a new self compensation scheme and applied it to a 10-bit D/A converter. This circuit can compensate the device mismatch without interrupting the D/A converter operation. With the compensation circuit,INA decreased down to 0.22LSB from 0.47LSB. The device was fabricated using a 0.8$\mu$m CMOS process. The area of the D/A converter core is 3.2mm$^{2}$ and the area of the compensation part is 0.64mm$^{2}$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.82-88
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• 1996

A simpel formular is proposed for the analysis of gate delay of CMOS gate in the low V$_{GS}-V_{TH}$ scaling. The effects of magnitude of V$_{GS}-V_{TH}$ on gate delay can be readily found through the formula so that it can be used ot design the device parameters in the low V$_{DD}$ CMOS circuits. The measured sresutls confirm the usability of the proposed formula and quantifies the improtance of V$_{TH}$ effects on gate delay under low voltae operation. Applying the formula to the prototype NMOSFET devices representing the five generations of technology, the impacts of the V$_{GS}-V_{TH}$ on the various aspects of the circuit and device characteristics are investigated in a consistent manner.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.112-120
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• 1996

With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.4
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• pp.30-39
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• 1998

Currently, LAMA(Local Automatic Message Accounting) is a billing mechanism which is being used for billing process, in which billing dat is written on MT(Magnetic Tape), collected at each regional billing center and then processed once a month. However, in order to prepare further development of telecommunication network and future new services, computerization of billing process and new daily billing processing system are urgently needed. Therefore Korea Telecom had developed a CAMA (Centralized Automatic Message Accounting) system for M10CN switch. In the CAMA system, billing data generated in switches is transfered on-line using approproate protocols and various transmission media and immediately processed. The CAMA system for M10CN switch consists of three parts such as ED (Extraction Device), TD(Transmission Device) and HC(Host Collector). The system also has redundancy to maintain continuance and confidence of system operation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.4
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• pp.40-50
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• 1993

In this paper, MODFET devices with various gate length are simulated using the Monte-Carlo method. The number of superparticle is 5000 and the Poisson equation is solved to obtain field distribution. The structure of MODFET is n-AlGaAs/i-AlGaAs/iGaAs and doping concentration of n-AlGaAs layer is 1${\times}10^{17}/cm^{3}$ and the thickness is 500.angs., and the thickness of i-AlGaAs is 50$\AA$. The devices with gate length 0.2$\mu$m, 0.5$\mu$m, 1.0$\mu$m respctively are simulated and the current-voltage curves and transport characteristics of that devices are obtained. Occupancy of each subband and electron energy distribution and conduction energy band in channel have been analyzed to obtain transport characteristics, and particles transposed from source to drain have been analyzed to current-voltage curves. Current level is highest for the device of Lg=0.2$\mu$m and transconductance of this device is 310mS/mm.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.60-68
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• 1993

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.794-803
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• 1987

In this paper, the SPICE 2.G6 JFET subroutine and other related subroutines are modified for circuit simulation of GaAs MESFET IC's. The hyperbolic tangent model is used for the drain current-voltage characteristics of GaAs MESFET's and derived channel-conductance and drain-conductance model from the above current model are implemented into small-signal model of GaAs MESFET's. And, device capacitance model which consider after-pinch-off state are modified, and device charge model for SPICE 2G.6 are proposed. The result of modification is shown to be suitable for GaAs circuit simulator, showing good agreement with experimetal results. Forthermore the DC convergence of this paper is better than that of SPICE 2.G JFET subroutine. GaAs MESFET model in this paper is applied for both depletion mode GaAs MESFET and enhancement-mode GaAs MESFET without difficulty.

• The KIPS Transactions:PartC
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• v.13C no.5 s.108
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• pp.641-650
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• 2006

There has been a continued increase in the complexity of software equipped with wireless mobile devices, due to the introduction of new device functionality and services via network connection. The increasement expected to be accelerated by convergence of telecommunication and broadcasting, and proliferation of telematics and home networking services using wireless mobile devices. The higher the complexity of mobile device software, the higher the necessity of management for the software. As for the global standard of mobile device management technology, OMA DM has been widely adopted by device manufacture and expected to be accelerated its adoption. In this paper, we present a development result of mobile device software release management system ThinkSync DM SoftMan. The implementation details of ThinkSync DM SoftMan are provided in implementation architecture and its working scenario based on the design of ThinkSync DM SoftMan that is summarized in this paper as our previous work. The conformance and performance test of the system are presented.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.11
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• pp.902-909
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• 1991

A reproducible selective dry etch process of GaAs/AlGaAs Heterostructures for High Electron Mobility Transistor(HEMT) Device fabrication is developed. Using RIE mode with $CCl_{2}F_{2}$ as the basic process gas, the observed etch selectivity of GaAs layer with respect to GaAs/$Al_{0.3}Ga_{0.7}$As is about 610:1. Severe polymer deposition problem, parialy generated from the use of $CCl_{2}F_{2}$ gas only, has been significantly reduced by adding a small amount of He gas or by $O_{2}$ plasma ashing after etch process. In order to obtain an optimized etch process for HEMT device fabrication, we com pared the properties of the wet etched Schottky contact with those of the dry etched one, and set dry etch condition to approach the characteristics of Schottky diode on wet etched surface. By applying the optimized etch process, the fabricated HEMT devices have the maximum transconductance $g_{mext}$ of 224 mS/mm, and have relatively uniform distribution across the 2inch wafer in the value of 200$\pm$20mS/mm.