• Journal of Electrical Engineering and Technology
• /
• 제10권1호
• /
• pp.280-287
• /
• 2015

Three-level PWM rectifiers applied in medium voltage applications usually operate at low switching frequency to keep the dynamic losses under permitted level. However, low switching frequency brings a heavy cross-coupling between the current components $i_d$ and $i_q$ with a poor dynamic system performance and a harmonic distortion in the grid-connecting current. To overcome these problems, a mathematical model based on complex variables of the three-level voltage source PWM rectifier is firstly established, and the reasons of above issues resulted from low switching frequency have been analyzed using modern control theory. Then, a novel control strategy suitable for the current decoupling control based on the complex variables for $i_d$ and $i_q$ is designed here. The comparisons between this kind of control strategy and the normal PI method have been carried out. MATLAB and experimental results are given in detail.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2003년도 International Symposium
• /
• pp.165-172
• /
• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Journal of Power Electronics
• /
• 제16권1호
• /
• pp.173-181
• /
• 2016

In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.

• 한국IT서비스학회지
• /
• 제7권1호
• /
• pp.255-274
• /
• 2008

The purpose of this research is to develop an information technology (IT) usage level assessment model for service industry. It is necessary to develop an assessment model for service industry's IT usage to improve service productivity. However, it is not easy to develop assessment models due to service industry's diversity. In this paper a generic IT usage assessment model for service industry has been developed and validated through a descriptive approach. Key factors affecting service productivity have been identified and analysed. A pilot test on IT usage level has been performed to investigate the relevance and importance of IT usage indicators (factors). As a result, a set of effective IT usage indicators for service industry have been found. A short-cut model and a full scale model have been proposed for efficient and effective usage. The results of this study can be used for enhancement of service industry productivity through the increase of IT usage level.

• 반도체디스플레이기술학회지
• /
• 제12권1호
• /
• pp.1-7
• /
• 2013

Grey-level statistical models have been widely used in many applications for object location and identification. However, conventional models yield some problems in model refinement when training images are not properly aligned, and have difficulties for real-time recognition of arbitrarily rotated models. This paper presents improved grey-level statistical models that align training images using image or feature matching to overcome problems in model refinement of conventional models, and that enable real-time recognition of arbitrarily rotated objects using efficient hierarchical search methods. Edges or features extracted from a mean training image are used for accurate alignment of models in the search image. On the aligned position and orientation, fitness measure based on grey-level statistical models is computed for object recognition. It is demonstrated in various experiments in PCB inspection that proposed methods are superior to conventional methods in recognition accuracy and speed.

• 한국경영과학회지
• /
• 제8권1호
• /
• pp.5-10
• /
• 1983

Foreign direct investment is considered to be one of the important technology transfer channels from advanced countries to less developed countries. The purpose of the study is to find the answers for the problems: if there is any difference of technology absorption level between the foreign affiliate companies, and what are the major factors which explain the difference. It is shown that the technology absorption level of foreign affiliate company is negatively related to the management control level by foreigners, to the rate of exportation, but positively related to the number of competing company and to the nature of generality of the technology.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2008년도 제39회 하계학술대회
• /
• pp.653-654
• /
• 2008

This paper presents a topological shape optimization for electromagnetic system using a level set method. The optimization is progressed by updating the implicit level set function from the Hamilton-Jacobi equation. The up-wind scheme is used for numerical implementation of the Hamilton-Jacobi equation. In order to validate the proposed optimization, the core part of a C-core actuator is optimized by three cases using different materials; (single steel), (two steels), and (steel and magnet).

• Journal of Power Electronics
• /
• 제13권1호
• /
• pp.86-93
• /
• 2013

A half-cycle-waveform inversion based three reference modulations seven-level SPWM (TRM-SPWM) scheme with one carrier is proposed in this paper. To keep the same comparison logics for the modulations and carrier during the negative half cycle and the positive one for the modulations, in the negative half cycle of the modulations, the DC offsets related to the amplitude of the carrier are set on the three modulations, respectively. The seven-level SPWM waveform with dead time thereby is implemented with only one Digital Signal Processor (DSP) without any other attached logic circuit. The basis principle of the proposed TRM-SPWM is analyzed in detail, and the frequency spectrums of the conventional and the proposed schemes are derived and compared with each other through simulation. The DSP based implementation is presented and detailed experimental waveforms verify the accuracy and feasibility of the proposed TRM-SPWM scheme.

• 반도체디스플레이기술학회지
• /
• 제14권4호
• /
• pp.72-77
• /
• 2015

Three-level diode clamped multilevel inverter, generally known as neutral point clamped (NPC) inverter, has an inherent problem causing neutral point (NP) potential variation. Until now, the NP potential problem of variation has been investigated and lots of solutions have also been proposed. This paper presents a neutral point voltage control technology using the anti-windup PI controller and offset technology of PWM (Pulse Width Modulation) to control the variation of NPC 3-phase three-level inverter neutral point voltage. And the proposed algorithm is tested and verified using a PLL (Phase Locked Loop) in order to synchronize the phase voltage from the line voltage of grid. It significantly improves the voltage balancing under a solar fluctuation conditions of the inverter. Experimental results show the good performance and effectiveness of the proposed method.

• 한국통신학회논문지
• /
• 제41권1호
• /
• pp.77-79
• /
• 2016

본 논문에서는 디지털 방송시스템의 전송방식에서 널리 사용 되고 있는 계층 변조 (Hierarchical Modulation)를 고려한다. 계층 변조기법은 다수의 독립적인 데이터 스트림의 송신 신호 전력을 조절하여 변조 심볼로 매핑하기 때문에 종래의 M-QAM에서 사용하는 정규화 인수 (Normalization Factor)를 사용할 수 없다. 본 논문에서는 3-level 계층 64QAM 기법의 정확한 정규화 인수를 구하기 위한 방법과 과정을 유도하여 제시한다.