• Journal of the Korean Graphic Arts Communication Society
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• v.18 no.1
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• pp.103-112
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• 2000

The color space transformation to link device-dependent color spaces and device-independent color spaces is essential for device characterization and cross-media color reproduction. There are various color conversion methods such as regression, 3D interpolation with LUT(look-up table), and neural network. In the color transformation with these methods, the conversion accuracy is essentially based on the sample data to be exploited for device characterization. In conventional method, color samples are uniformly selected in device-dependent space such as CMY and RGB. However, distribution of these color samples is very non-uniform in device-independent color space such as CIEL*a*b*. Accordingly, the conversion error in device-independent color space is irregular according to the distribution of the samples. In this paper, a color sampling method based on equi-visual perception is proposed to obtain approximate uniform color samples in CIEL*a*b* space. In order to evaluate transformation accuracy of proposed method, color space transformations are simulated using regression, 3D interpolation with LUT and neural network techniques, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1577-1580
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• 2004

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA) which is able to calculate the inner product by shifting and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.758-761
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• 2004

This paper proposes a design and implementation of multiplierless digital PID (Proportional-Integral-Derivative) controller using FPGA (Field Programmable Gate Array) for controlling the speed of DC motor in digital system. The multiplierless PID structure is based on Distributed Arithmetic (DA). The DA is an efficient way to compute an inner product using partial products, each can be obtained by using look-up table. The PID controller is designed using MATLAB program to generate a set of coefficients associated with a desired controller characteristics. The controller coefficients are then included in VHDL (Very high speed integrated circuit Hardware Description Language) that implements the PID controller onto FPGA. MATLAB program is used to activate the PID controller, calculate and plot the time response of the control system. In addition, the hardware implementation uses VHDL and synthesis using FLEX10K Altera FPGA as target technology and use MAX+plusII program for overall development. Results in design are shown the speed performance and used area of FPGA. Finally, the experimental results can be shown when compared with the simulation results from MATLAB.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.6
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• pp.3208-3229
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• 2017

Rectification is an essential procedure for simplifying the disparity extraction of stereo matching algorithms by removing vertical mismatches between left and right images. To support real-time stereo matching, studies have introduced several look-up table (LUT)- and computational logic (CL)-based rectification approaches. However, to support high-resolution images, the LUT-based approach requires considerable memory resources, and the CL-based approach requires numerous hardware resources for its circuit implementation. Thus, this paper proposes a multi-level accumulation-based rectification method as a simple CL-based method and its circuit implementation. The proposed method, which includes distortion correction, reduces addition operations by 29%, and removes multiplication operations by replacing the complex matrix computations and high-degree polynomial calculations of the conventional rectification with simple multi-level accumulations. The proposed rectification circuit can rectify $1,280{\times}720$ stereo images at a frame rate of 135 fps at a clock frequency of 125 MHz. Because the circuit is fully pipelined, it continuously generates a pair of left and right rectified pixels every cycle after 13-cycle latency plus initial image buffering time. Experimental results show that the proposed method requires significantly fewer hardware resources than the conventional method while the differences between the results of the proposed and conventional full rectifications are negligible.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.355-359
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• 2001

This paper presents an implementation of digital control system of speed sensorless for Reluctance Synchronous Motor (RSM) drives with DTC. The control system consists of stator flux observer, rotor position/speed/torque estimator, two hysteresis band controllers, an optimal switching look-up table, IGBT voltage source inverter, and TMS320C31 DSP controller by using fully integrated control software. The stator flux observer is based on the combined voltage and current model with stator flux feedback adaptive control that inputs are current and voltage sensing of motor terminal with estimated rotor angle for wide speed range. The rotor position is estimated by observed stator flux-linkage space vector. The estimated rotor speed is determined by differentiation of the rotor position used only in the current model part of the flux observer for a low speed operating area. It does not require the knowledge of any motor parameters, nor particular care for motor starting, In order to prove the suggested control algorithm, we have a simulation and testing at actual experimental system. The developed sensorless control system is shown a good speed control response characteristic results and high performance features in 50/1000 rpm with 1.0Kw RSM having 2.57 ratio of d/q reluctance.

• Journal of Information Display
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• v.3 no.4
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• pp.19-22
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• 2002

In this paper, we introduce an efficient three-dimensional magnetic field mapping system for a Deflection Yoke (DY) in Cathode-Ray Tube (CRT). A three-axis Hall probe mounted in a small cylindrical bar and three-stepping motors placed in a non-magnetic frame were utilized for the mapping. Prior to the mapping starts, the inner contour of DY was measured by a laser sensor to make a look-up table for inner shape of DY. Three-axis magnetic fields are then digitized by a three-dimensional Hall probe. The results of the mapping can be transformed into various output formats such as multi pole harmonics of magnetic fields. Field shape in one, two and three- dimensional spaces can also be displayed. In this paper, we present the features of this mapping device and some analysis results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1042-1047
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• 1999

In this paper, two kinds of digital predistorters are proposed and their performances are analyzed in order to minimize ACI and SNR degradation caused by nonlinearly amplified TC-16QAM signal and to transmit high speed data in power and bandwidth limited land mobile satellite channel. Our simulation results show that LUT predistorter reduces the out-of-band ACI more efficiently as compared to intersymbol interpolated predistorter. Regarding the reduction of in-band SNR and total power intersymbol interpolated predistorter outperforms LUT predistorter. In the simulation mobile satellite channel and nonlinear HPA are modeled by Rician channel and Fujitsu SSPA, respectively.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.23-26
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• 2001

This paper presents a digital motion control system for Reluctance Synchronous Motor (RSM) drives with direct torque control (DTC). The system consists of stator flux observer, torque estimator: two hysteresis band controllers, an optimal switching look-up table, IGBT voltage source inverter(VSI), and TMS320C31 DSP controller by using fully integrated control software. The stator flux observer is based on the combined voltage and current model with stator flux feedback adaptive control of which inputs are current, voltage and actual rotor angle for wide speed range. In order to prove the suggested motion control algorithm, There are some simulation and testing at actual experimental system. The developed digitally high-performance motion control system are shown a good motion control response characteristic results and high performance features using 1.0Kw RSM.

• Journal of Korea Multimedia Society
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• v.5 no.6
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• pp.609-615
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• 2002

In this paper, we propose a contrast for the improvement of multi-gray scale image on display system. The proposed method distinguishes a maximum value and a minimum value in input fields or frames. By this judgement, the improvement degree of image quality is decided. This method does not require field and frame memory. Moreover, its lower hardware complexity than conventional methods make it easy to apply this method for flat panel display(FPD) which requires real-time processing. And the contrast of input gray level can be controled flexibly by varying the weight the weight value which controls the contrast range. The proposed method gives an image by controlling weighting slope selectively at intervals according to the brightness-control algorithm and the type of image in the look-up table. The function of the proposed method has been verified through Synopsys VHDL and computer simulation. And its results show that the proposed method can improve the quality of image.