• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.10-10
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• 2010

ESD (Electrostatic Discharge) phenomenon occurs in everywhere and especially it damages to semiconductor devices. For ESD protection, there are some devices such as diode, GGNMOS (Gate-Grounded NMOS), SCR (Silicon-Controlled Rectifier), etc. Among them, diode and GGNMOS are usually chosen because of their small size, even though SCR has greater current capability than GGNMOS. In this paper, a novel SCR is proposed on the SOI (Silicon-On-Insulator) structure which has $1{\mu}m$ film thickness. In order to design and confirm the proposed SCR, TSUPREM4 and MEDICI simulators are used, respectively. According to the simulation result, although the proposed SCR has more compact size, it's electrical performance is better than electrical characteristics of conventional GGNMOS.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.193-196
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• 2002

This paper presents the improvement of the boron penetration and the reverse short channel effect (RSCE) in the 130nm W/WNx/Poly-Si dual gate PMOSFET for a high performance embedded DRAM. In order to suppress the boron penetration, we studied a range in the process heat budget. It has shown that the process heat budget reduction results in suppression of the boron penetration. To suppress the RSCE, we experimented with the halo (large tilt implantation of the same type of impurities as those in the device well) implant condition near the source/drain. It has shown that the low angle of the halo implant results in the suppression of the RSCE. The experiment was supported from two-dimensional(2-D) simulation, TSUPREM4 and MEDICI.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.95-98
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• 2003

Power semiconductors are being currently used as a application of intelligent power inverters to a refrigerator, a washing machine and a vacuum cleaner as well as core parts of industrial system. The rating of semiconductor devices is an important factor in decision on the field of application and the forward blocking voltage is one of factors in decision of the rating. The Power MOS device has a merit of high input impedance, short switching time, and stability in temperature as well known. Power MOS devices are mainly used as switches in the field of power electronics, especially the on-state resistance and breakdown voltage are regarded as the most important parameters. Power MOS devices that enable a small size, a light weight, high-integration and relatively high voltage are required these days. In this paper, we proposed the new lateral power MOS which has forward blocking voltage of 250V and contains trench electrodes and verified manufactural possibility by using TSUPREM-4 that is process simulator.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.164-167
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• 1994

In this Study, we design the process of 0.1$\mu\textrm{m}$ gate length CMOS that is immunized against Latch-up, and investigate the characteristic of Latch-up of this device by the design rule of layout. Using TSUPREM4 and MEDICI, we design the device and simulate the variable characteristics of it we could understand that the characteristic of Latch-up is changed for the better by varying the critical factor of it. We also investigate the structure of CMOS that can be immunized against Latch-up.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.9
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• pp.605-610
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• 1999

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.1
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• pp.27-30
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• 2004

In this paper, a new small size Lateral Trench Electrode Power MOSFET is proposed. This new structure, called "LTEMOSFET"(Lateral Trench Electrode Power MOSFET), is based on the conventional MOSFET. The entire electrode of LTEMOSFET is placed in trench oxide. The forward blocking voltage of the proposed LTEMOSFET is improved by 1.6 times with that of the conventional MOSFET. The forward blocking voltage of LTEMOSFET is 250V. At the same size, a increase of the forward blocking voltage of about 1.6 times relative to the conventional MOSFET is observed by using TMA-MEDICI which is used for analyzing device characteristics. Because the electrodes of the proposed device are formed in trench oxide, the electric field in the device are crowded to trench oxide. We observed that the characteristics of the proposed device was improved by using TMA-MEDICI and that the fabrication of the proposed device is possible by using TMA-TSUPREM4.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.176-184
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• 1996

To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.9
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• pp.671-676
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• 2012

In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.323-326
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• 2003

In this paper, a new small size Lateral Trench Electrode Power MOSFET is proposed. This new structure, called "LTEMOSFET"(Lateral Trench Electrode Power MOSFET), is based on the conventional MOSFET. The entire electrode of LTEMOSFET is placed in trench oxide. The forward blocking voltage of the proposed LTEMOSFET is improved by 1.6 times with that of the conventional MOSFET. The forward blocking voltage of LTEMOSFET is 250V. At the same size, a increase of the forward blocking voltage of about 1.6 times relative to the conventional MOSFET is observed by using TMA-MEDICI which is used for analyzing device characteristics. Because the electrodes of the proposed device are formed in trench oxide, the electric field in the device are crowded to trench oxide. We observed that the characteristics of the proposed device was improved by using TMA-MEDICI and that the fabrication of the proposed device is possible by using TMA-TSUPREM4.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.11
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• pp.1156-1166
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• 2004

Antimony profiles by MeV implantation are measured by secondary ion mass spectrometry (SIMS) and spreading resistance (SR). The moments of SIMS and simulated profiles are calculated and compared for the exact range in MeV energy. SRIM, DUPEX, ICECREM, and TSUPREM4 simulation programs are used for the calculation of range 1D, 2D. SRIM is a Monte Carlo simulation program and different inter-atomic potentials can be used for the calculation of nuclear stopping power cross-section (Sn) and range moments. Nevertheless, the range parameters were not influenced from nuclear stopping power in MeV. Through the modification of electronic stopping power cross-section (Se), the results of simulation are remarkably improved and matched very well with SIMS data. The values of electronic stopping power are optimized for Sb high energy implantation. For the electrical activation, Sb implanted samples are annealed under $N_2$ and $O_2$ ambient. Finally, Oxidation retard diffusion(ORD) effect of Sb implanted sample are demonstrated by SR measurements and ICECREM simulation.