• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.90-97
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• 2006

In this paper, we present a cost-effective architecture of high-speed soft-decision Viterbi decoder for Multi-band OFDM(MB-OFDM) systems. In the design of modem for MB-OFDM systems, a parallel processing architecture is general]y used for the reliable hardware implementation, because the systems should support a very high-speed data rate of at most 480Mbps. A Viterbi decoder also should be designed by using a parallel processing structure and support a very high-speed data rate. Therefore, we present a optimized hardware architecture for 4-way parallel processing Viterbi decoder in this paper. In order to optimize the hardware of Viterbi decoder, we compare and analyze various ACS architectures and find the optimal one among them with respect to hardware complexity and operating frequency The Viterbi decoder with a optimal hardware architecture is designed and verified by using Verilog HDL, and synthesized into gate-level circuits with TSMC 0.13um library. In the synthesis results, we find that the Viterbi decoder contains about 280K gates and works properly at the speed required in MB-OFDM systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.384-390
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• 2008

Chaotic OOK modulation method can be used in LDR(Low Data Rate) UWB systems. In this paper, UWB chaotic-OOK transmitter system is designed and verified using TSMC 0.18 um CMOS process. A transmitter system is composed of Quasi-chaotic signal generator, OOK Modulator, and driving amplifier. The traditional chaotic signal generators using analog feedback method is weak to process variation. In order to solve this problem, a quasi-chaotic signal generator using digital feedback technique is get wide band signal and OOK Modulator using T-type switching structure is used to enhance the isolation characteristic. A driving amplifier has differential to single structure to avoid an external balun for low cost communication. The measured output power spectrum of the transmitter meet the FCC regulation and the result of the modulation test at data rate of 20 Kbps, 200 Kbps, 2 Mbps, and 10 Mbps is conformed to LDR UWB system. It is shown that the transmitter in this paper can be used for the UWB chaotic-OOK system.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.169-177
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• 2012

A non-decimation second-order spatial moving average (SMA) discrete-time (DT) filter is proposed with reconfigurable null frequencies. The filter coefficients are changeable, and it can be controlled by switching sampling capacitors. So, interferers can be rejected effectively by flexible nulls. Since it operates without decimation, it does not change the sample rate and aliasing problem can be avoided. The filter is designed with variable weight of coefficients as $1:{\alpha}:1$ where ${\alpha}$ varies from 1 to 2. This corresponds to the change of null frequencies within the range of fs/3~fs/2 and fs/2~2fs/3. The proposed filter is implemented in the TSMC 0.18-${\mu}m$ CMOS process. Simulation shows that null frequencies are changeable in the range of 0.38~0.49fs and 0.51~0.62fs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.53-58
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• 2008

This paper proposes a new set of instructions to improve the packet processing capacity of a network processor. The proposed set of instructions is able to achieve more efficient packet processing by accelerating integration of packet headers. Furthermore, a hardware configuration dedicated to processing overlay instructions was designed to reduce additional hardware cost. For this purpose, the basic architecture for the network processor was designed using LISA and the overlay block was optimized based on the barrel shifter. The block was synthesized to compare the area and the operation delay, and allocated to a C-level macro function using the compiler known function (CKF). The improvement in performance was confirmed by comparing the execution cycle and the execution time of an application program. Experiments were conducted using the processor designer and the compiler designer from Coware. The result of synthesis with the TSMC ($0.25{\mu}m$) from Synopsys indicated a reduction in operation delay by 20.7% and an improvement in performance of 30.8% with the proposed set of instructions for the entire execution cycle.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.1045-1049
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• 2010

In this paper, we proposed an ultra-low power low noise amplifier(LNA) using a TSMC 0.18 ${\mu}m$ RF CMOS process. To satisfy the low power consumption with high gain, a current-reused technique is utilized. In addition, a low bias voltage in the subthreshold region is utilized to achieve ultra low power characteristic. The designed LNA has the voltage gain of 13.8 dB and noise figure(NF) of 3.4 dB at 2.4 GHz. The total power consumption of the designed LNA is only 0.63 mW from 0.9 V supply voltage and chip occupies $1.1\;mm{\times}0.8\;mm$ area.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.848-851
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• 2012

In this paper, circuit of reducing the offset voltage in Op-amp, effectively, is newly proposed by using dual capacitor. Capacitors and MOS switches are added in proposed circuit to make up for the weak points of previous circuits ofr reducing the offset voltage in auto-zeroing method. Also, it is designed to reduce the offset voltage in high frequency range by using chopping method, effectively. Circuit simulation and layout are executed by TSMC 1.8V, 0.18um process. From the simulation results, it is verified that magnitude of offset voltage is under 5mV and proposed circuit is good for compensation of offset voltage better than previous auto-zeroing method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.99-102
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• 2012

An image scaler is a IP used in a image processing block of display devices to adjust image size. Proposed image scaler adopts line memories instead of a conventional method using a frame memory. This method reduced hardware resources and enhanced data precision by using shift operations that number is multiplied by $2^m$ and divided again at final stage for scaling. Also image scaler increased efficiency of IP by using serial divider to calculate parameters by itself. Parameters used in image scaling is automatically produced by it. Suggested methods are designed by Verilog HDL and implemented with Xilinx Vertex-4 XC4LX80 and ASIC using TSMC 0.18um process.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.125-131
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• 2010

This paper presents the implementation of a EBCOT TIER-1 for JPEG2000 Encoder. JPEG2000 is new standard for the compression of still image for overcome the artifact of JPEG. JPEG2000 standard is based on DWT(Discrete Wavelet Transform) and EBCOT Entropy coding technology. EBCOT(Embedded block coding with optimized truncation) is the most important technology that is compressed the image data in the JPEG2000. However, EBCOT has the artifact because the operations are bit-level processing and occupy the harf of the computation time of JPEG2000 Compression. Therefore, in this paper, we present modified context extraction method for enhance EBCOT computational efficiency and implemented MQ- Coder as arithmetic coder. The proposed system is implemented by Verilog-HDL, under the condition of TSMC 0.25um ASIC library, gate counts are 30,511EA and satisfied the 50MHz operating condition.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.201-207
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• 2008

This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.124-129
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• 2013

This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.