• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2045-2049
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• 2008

In this paper, we propose an novel architecture for H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18 um process including SRAM memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1605-1614
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• 2008

This paper proposed a new VLSI architecture of motion estimation (ME) and compensation (MC) for efficient video compression and implemented it to hardware. ME is generally calculated using SAD result. So we proposed a new arithmetic method for SAD. The proposed SAD calculation method increases arithmetic efficiency and decreases external memory usage. Finally it increases performance of ME/MC. The proposed ME/MC hardware was implemented to ASIC with TSMC 90nm HVT CMOS library. The implemented hardware occupies about 330K gates and stably operates the clock frequency of 143MHz.

• International Area Studies Review
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• v.20 no.2
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• pp.85-111
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• 2016

Global semiconductor companies is investing enormous capital worldwide. And direct investment in China is increasing greatly these days, Especially, global semiconductor companies are setting up a factory in China due to expanding market rather than utilizing low labor cost. Therefore, this study is trying to analyze the background and process of direct investment from global Korean and Taiwanese semiconductor companies in China. Firstly, In 1996, Samsung semiconductor established a back end process factory in Suzhou. And in 2014, Samsung semiconductor set up a front and back end factory in Xian. Secondly, In 2006, SK Hynix built a front and back end factory in Wuxi. and SK Hynix set up a back end factory named Hitech semiconductor with Chinese company in 2009. Later in 2015, SK Hynix established a back end factory in Chongqing. Thirdly, In 2004, TSMC started to operate a factory in Shanghai, and in 2018, TSMC is going to establish a factory in Nanjing. Lastly, UMC bought a stock to produce product in Chinese local company named HJT, and at the end of 2016, UMC is going to finish building a factory in Xiamen. As a result, it was proved that most companies hoped to expand the chinese market by setting up a factory in china. In addition, Samsung expected to avoid a risk by setting up a factory in china, and SK Hynix wanted to avoid a countervailing duty by setting up a factory in china. Based on the result of this study, this study indicates some implications for other semiconductor companies which are very helpful for their future foreign direct investment.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.373-376
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• 2004

The measurement of diffraction of LCOS microdisplay with various pixel size, interpixel gap, pixel height and coatings demonstrates that pixel size is the leading factor for diffraction loss, while the role of varying pixel gap is less significant comparatively. One-dimensional diffraction simulation is found to be in good agreement with the measurement. Noticeable deviation occurs when pixel size is as small as 8um.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.531-532
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• 2008

In this paper, we present the comparison of the CMOS Double-Balanced Mixer for WLAN applications using the tail current source and not using it at the same current. The mixers are derived from the Gilbert cell mixer and have been simulated by using TSMC $0.18{\mu}m$ RF CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.7
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• pp.3425-3430
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• 2013

The fast-growing market in wireless communications has led to the development of multi-standard mobile terminals. In this paper, a frequency-tunable active RC bandpass filter for multi-standards wireless communication system is designed using an active inductor. The conventional bandpass filter design methods employ the high order filter or high quality factor Q to improve the stopband attenuation characteristics and frequency selectivity of the passband. The proposed bandpass filter based on the high Q active inductor has an improved frequency characteristics. The center frequency and gain of the designed bandpass filter is tuned by employing the tuning circuit. We have performed the simulation using TSMC $0.18{\mu}m$ process parameter to analyze the characteristics of the designed active RC bandpass filter. The bandpass filter with Q=20.5 has 90MHz half power bandwidth at the center frequency of 1.86GHz. Moreover, the center frequency of the proposed bandpass filter can be tuned between 1.86~2.38GHz for the multi-standards wireless communication system using the capacitor of the tuning circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.361-366
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• 2012

This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.78-83
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• 2014

This paper suggest an effective idea to implement an low area multi-mode one dimension transform block of HEVC(High Efficiency Video Coding). The time consuming multiplier path is designed to operate on low frequency. Normal multipliers dealing with variable operands are replaced with smaller constant multipliers which do the product with constant coefficient and variable only using shifters and adders. This scheme increases total multiplier counts but entire areas are reduced owing to smaller area of constant multiplier. Idle cycles caused by doubled multipliers enable to use multi-cycle paths on the cycle eating multiplier data path. Operating frequency is lowered by multi-cycle path but total throughput is maintained. This structure is implemented with TSMC 0.18 CMOS process library, and operated on 186MHz frequency to process a 4k($3840{\times}2160$) image. Max operating frequency is 300MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.