• Journal of Computing Science and Engineering
• /
• v.6 no.2
• /
• pp.105-118
• /
• 2012

We propose two new approaches that automatically parallelize Java programs at runtime. These approaches, which rely on run-time trace information collected during program execution, dynamically recompile Java byte code that can be executed in parallel. One approach utilizes trace information to improve traditional loop parallelization, and the other parallelizes traces instead of loop iterations. We also describe a cost/benefit model that makes intelligent parallelization decisions, as well as a parallel execution environment to execute parallelized programs. These techniques are based on Jikes RVM. Our approach is evaluated by parallelizing sequential Java programs, and its performance is compared to that of the manually parallelized code. According to the experimental results, our approach has low overheads and achieves competitive speedups compared to the manually parallelizing code. Moreover, trace parallelization can exploit parallelism beyond loop iterations.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.1
• /
• pp.75-80
• /
• 1995

In this paper, we show that it is more efficient to use a new algorithm than to use a method of trace definition and property when we use trace calculation method on trinomial irreducible polynomial of reed-solomon code. This implementation has been done in SUN SPARC2 workstation using C-language.

• Transactions of the Korean Society of Pressure Vessels and Piping
• /
• v.20 no.1
• /
• pp.32-38
• /
• 2024

The best estimate plus uncertainty methodologies for loss-of-coolant accident analyses make use of the best-estimate codes and relevant experimental databases. Inherently, best-estimate codes have various uncertainties in the model parameters, which can be quantified by the dedicated experimental database. Therefore, this study was devoted to establishing procedures for identifying the input parameters of predictive models and quantifying their uncertainty ranges. The rod bundle heat transfer experiments were employed as a representative reflood separate effect test, and the TRACE code was utilized as a best-estimate code. In accordance with the present procedure for uncertainty quantification, the integrated list of the influential input parameters and their uncertainty ranges was obtained through local sensitivity calculations and screening criteria. The validity of the procedure was confirmed by applying it to uncertainty analyses, which checks whether the measured data are within computed ranges of the variables of interest. The uncertainty quantification procedure proposed in this study is anticipated to provide comprehensive guidance for the conduct of uncertainty analyses.

• Journal of the Institute of Convergence Signal Processing
• /
• v.13 no.4
• /
• pp.194-200
• /
• 2012

In this paper we analyze the code sequence generating algorism defined on $GF(2^n)$ proposed by S.Bostas and V.Kumar[7] and derive the implementation functions of code sequence generator using Boolean functions which can map the vector space $F_2^n$ of all binary vectors of length n, to the finite field with two elements $F_2$. We find the code sequence generating boolean functions based on two kinds of the primitive polynomials of degree, n=5 and n=7 from trace function. We then design and implement the code sequence generators using these functions, and produce two code sequence groups. The two groups have the period 31 and 127 and the magnitudes of out of phase(${\tau}{\neq}0$) autocorrelation and crosscorrelation functions {-9, -1, 7} and {-17, -1, 15}, satisfying the period $L=2^n-1$ and the correlation functions $R_{ij}({\tau})=\{-2^{(n+1)/2}-1,-1,2^{(n+l)/2}-1\}$ respectively. Through these results, we confirm that the code sequence generators using boolean functions are designed and implemented correctly.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2006.07a
• /
• pp.573-573
• /
• 2006

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.1
• /
• pp.36-44
• /
• 2003

This paper proposes a Viterbi decoding scheme without trace-back operations to reduce the amount of memory storing the survivor path information, and to increase the decoding speed. The proposed decoding scheme is a modified register exchange scheme, and is verified by a simulation to give the same results as those of the conventional decoders. It is compared with the conventional decoding schemes such as the trace-back and the register exchange scheme. The memory size of the proposed scheme is reduced to 1/(5 x constraint length) of that of the register exchange scheme, and the throughput is doubled compared with that of the trace-back scheme. A decoder with a code rate of 2/3, a constraint length, K＝3 and a trace-back depth of 15 is designed using VHDL and implemented in an FPGA. It is also shown that the modified register exchange scheme can be applied to a block decoding scheme.

• Convergence Security Journal
• /
• v.18 no.5_1
• /
• pp.19-24
• /
• 2018

For a long time now, general-purpose processors have provided dedicated hardware / software tracing modules to provide developers with tools to fix bugs. A hardware tracer generates its enormous data into a log that is used for both performance analysis and debugging. Processor Trace (PT) is a new hardware-based tracing feature for Intel CPUs that traces branches executing on the CPU, which allows the reconstruction of the control flow of all executed code with minimal labor. Hardware tracer has been integrated into the operating system, which allows tight integration with its profiling and debugging mechanisms. However, in the Windows environment, existing studies related to PT focused on decoding only one flow in sequence. In this paper, we propose an extended PT decoder structure that provides basic data for real-time trace and malicious code detection using the functions provided by PT in Windows environment.

• Convergence Security Journal
• /
• v.19 no.1
• /
• pp.97-101
• /
• 2019

If the operating system's core file contains an Intel PT, the debugger can not only check the program state at the time of the crash, but can also reconfigure the control flow that caused the crash. We can also extend the execution trace scope to the entire system to debug kernel panics and other system hangs. The second-generation PT, the WinIPT library, includes an Intel PT driver with additional code to run process and core-specific traces through the IOCTL and registry mechanisms provided by Windows 10 (RS5). In other words, the PT trace information, which was limited access only by the first generation PT, can be executed by process and core by the IOCTL and registry mechanism provided by the operating system in the second generation PT. In this paper, we compare and describe methods for collecting, storing, decoding and detecting malicious codes of data packets in a window environment using 1/2 generation PT.

• Nuclear Engineering and Technology
• /
• v.44 no.7
• /
• pp.719-726
• /
• 2012

The object of this work is the validation and assessment of the TRACE v5.0 code using the scaled test ATLAS1 facility in the context of a DVI2 line break. In particular, the experiment selected models the 50%, 6-inch break of a DVI line. The same experiment was also adopted as a reference test in the ISP-503. The ISP-50 was proposed to, and accepted by, the OECD/NEA/CSNI due to its technical importance in the development of a best-estimate of safety analysis methodology for DVI line break accidents. In particular, the behavior of the two-phase flow in the upper annulus downcomer was expected to be complicated. What resulted was the need for relevant models to be implemented into safety analysis codes, in order to predict these thermal hydraulic phenomena correctly.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11C
• /
• pp.1045-1051
• /
• 2003

The SOVA, which produces the soft decision value, can be used as a sub-optimum solution for concatenated codes such as turbo codes, since it is computationally efficient compared with the optimum MAP algorithm. In this paper, we propose an efficient implementation of the SOVA used for decoding turbo codes, by reducing the number of calculations for soft decision values and trace-back operations. In order to utilize the memory efficiently, the whole block of turbo codes is divided into several sub-blocks in the proposed algorithm. It is demonstrated that the proposed algorithm requires less computation than the conventional algorithm, while providing the same overall performance.