• Proceedings of the KIPE Conference
• /
• 2012.11a
• /
• pp.88-90
• /
• 2012

A study on an integrated single stage AC/DC converter is presented in this paper. The input current can be controlled by the auxiliary winding($L_{aux}$), auxiliary primary winding($N_3$), and the boost inductor($L_B$) which are designed to operate in discontinuous conduction mode(DCM) to reduced the total harmonic distortion(THD) of input current. The auxiliary primary winding($N_3$) is critically selected in order to compress the input capacitor voltage($V_{in}$) as well as to reduce the current stress of the switch(Q). Low total harmonic distortion(THD), low input voltage($V_{in}$) in universal input voltage($V_{AC}$), low current stress at the switching device and high efficiency are the main consideration keys in this design to achieve high performance system with low cost of single stage AC/DC converter. A 30W single stage AC/DC prototype converter is under study.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.38 no.5
• /
• pp.52-58
• /
• 2001

In this paper, the low voltage linear tunable transconductors using the series composite transistor are presented. Due to the series composite transistor operating in the saturation region and the triode region, the proposed circuits have wide input range at low supply voltage. The designed transconductors have been simulated by HSPICE using $0.25{\mu}m$ n-welll CMOS process. Simulation results show that the cutoff frequency is 309M Hz and the THD of less than 1.1% can be obtained for the differential input signal of up to l.5VP-P with the input signal frequency of l0MHz.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.13 no.6
• /
• pp.55-61
• /
• 2013

In this paper, we describe design and implementation of audio encoder/decoder for voice synthesis. It uses the encoding of difference value of successive samples instead of the original sample value. and has the compression ratio of 4. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 16.384MHz. The measured THD+n is from -40dB to -80dB with frequency variation and the power consumption is about 80mW. It is suited for the mobile application of high audio quality and low power consumption.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.11
• /
• pp.57-62
• /
• 1998

In this paper, tunable transconductor shows good linearity over a wide input voltage range are proposed. The proposed transconductor employ operating in the nonsaturation(ie., linear) region to improve circuit simplicity and tunability and 6.8V$\_$p-p/ wide input range. Also the circuit employ source-coupled differential pair to provide true differential input and can achieve both positive and negative transconductance values. The proposed circuits are implemented using a 1.2 $\mu\textrm{m}$ single poly double metal n-well CMOS technology. The THD characteristic of proposed circuit is less than 1% for a differential input voltage of up to 6V$\^$p-p/ when supply bias condition is V$\_$DD/=-V$\_$ss/=5V, I$\_$B/=20, 40${\mu}$A, and frequency of input signal is 1KHz.

• Journal of Broadcast Engineering
• /
• v.21 no.5
• /
• pp.792-802
• /
• 2016

Real time verification is necessary, since there are several features that cannot be verified through design simulation in the design of multiband soundbar system. And then this paper describes an implementation of an FPGA-based real-time verification system for a soundbar SoC with an embedded processor. It is verified a real-time performance test and a listening test which are several features in the design stage that cannot be verified through a design simulation. The measurement of quantitative specifications such as SNR, THD+N, frequency response, etc. as well as the listening test were performed through the implemented FPGA system, and it was verified that test results satisfied the target specifications.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.4
• /
• pp.285-296
• /
• 2017

This paper proposes an improved modulation scheme for the medium voltage modular multi-level converter (MMC), which operates in the nearest level control and applies in the medium voltage direct current (MVDC) system. In the proposed modulation scheme, the offset (neutral-to-zero output) voltage is adjusted, with the phase voltage magnitude, thereby maintaining a constant value with N+1 level in the controllable modulation index (MI) range. In order to confirm the proposed scheme's validity, computer simulations for the 22.9 kV - 25 MVA MMC were performed with PSCAD/EMTDC, as well as hardware experiments for the 380 V - 10 kVA MMC. The proposed modulation scheme offers to build a constant pole voltage regardless of the MI value, and to build a phase voltage with improved total harmonic distortion (THD).

• Proceedings of the KIPE Conference
• /
• 2012.11a
• /
• pp.109-110
• /
• 2012

본 논문에서는 불평형 전원 전압 하에서 삼상 PWM 컨버터의 전류 보상 기법을 제안하였다. 전원 전압이 불평형인 경우 PLL(Phase Locked Loop)를 이용하여 추출한 위상각에는 왜곡 성분이 포함된다. 이러한 왜곡된 위상각으로 컨버터를 제어하는 경우 입력 전류에도 고조파가 포함되게 된다. 본 논문에서는 불평형 전원 전압 하에서도 입력 전류의 THD(Total Harmonic Distortion)를 IEEE Std. 519 규정인 5% 이내로 제한할 수 있도록 하는 전류 보상 기법을 제안하였다. 제안된 기법은 시뮬레이션을 통해 그 타당성을 검증하였다.

• Journal of applied mathematics & informatics
• /
• v.6 no.3
• /
• pp.757-770
• /
• 1999

We analyse in this paper the possibility of using preconditioning techniques as for square non-singular systems, also in the case of inconsistent least-squares problems. We find conditions in which the minimal norm solution of the preconditioned least-wquares problem equals that of the original prblem. We also find conditions such that thd Kaczmarz-Extendid algorithm with relaxation parameters (analysed by the author in [4]), cna be adapted to the preconditioned least-squares problem. In the last section of the paper we present numerical experiments, with two variants of preconditioning, applied to an inconsistent linear least-squares model probelm.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.244-247
• /
• 1999

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of a pair of transconductor and lowers supply voltage down to $V_{T}$+2 $V_{Ds,sat}$+ $V_{DS,triode}$. The designed analog four-quadrant multiplier have simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7 $V_{p-p}$././.

• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.271-273
• /
• 2007

본 논문에서는 TV나 Audio등에 사용되는 2채널 30W급 Class-D amplifier를 동부하이텍의 0.35um BD350BA 공정을 사용하여 디지털 방식의 Class-D amplifier 출력단 구동에 적합하도록 설계하였다. 출력단은 Bootstrap 전원을 사용한 N-N type의 30V LDMOS 내장형이며 각각 $250m{\Omega}$의 턴 온 저항을 갖게 설계 되었다. THD+N 특성개선을 위한 Dead time 및 Delay 조정회로를 내장하였으며 보호회로로는 Over current, Over temperature, UVLO 가 있다.