• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.695-698
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• 2005

The finite-field multiplication can be applied to the wide range of applications, such as signal processing on communication, cryptography, etc. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cell, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-serial and digit-serial multipliers, the proposed multiplier shows relatively better performance with low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.3
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• pp.61-67
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• 2003

We propose a systolic array for dynamic programming which is a technique for solving combinatorial optimization problems. We derive a systolic array for single source shortest path Problem, SA SSSP, and then show that the systolic array serves as dynamic Programming systolic array which is applicable to any dynamic programming problem by developing a systolic array for 0 1 knapsack problem, SA 01KS, with SA SSSP for a basis. In this paper, each of SA SSSP and SA 01KS is modeled and simulated in RT level using VHDL, then synthesized to a schematic and finally implemented to a layout using the cell library based on 0.35${\mu}{\textrm}{m}$ 1 poly 4 metal CMOS technology.

• Journal of information and communication convergence engineering
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• v.14 no.1
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• pp.26-34
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• 2016

The alignment of DNA sequences is one of the important processes in the field of bioinformatics. The Smith-Waterman algorithm (SWA) performs optimally for aligning sequences but is computationally expensive. Field programmable gate array (FPGA) performs the best on parameters such as cost, speed-up, and ease of re-configurability to implement SWA. The performance of FPGA-based SWA is dependent on efficient cell-basic implementation-unit design. In this paper, we present an optimized systolic cell design while avoiding oversimplification, very large-scale integration (VLSI)-level design, and direct mapping of iterative equations such as previous cell designs. The proposed design makes efficient use of hardware resources and provides portability as the proposed design is not based on gate-level details. Our cell design implementing a linear gap penalty resulted in a performance improvement of 32× over a GPP platform and surpassed the hardware utilization of another implementation by a factor of 4.23.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.648-658
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• 1990

There are many methods for speed up counting in speech recongition. A multiple processing method is the one way to achieve the aim using systolic array. This arithmetic operation by the array is achieved pipelining skill. And the operation is multiprocessing by processing element(PE) that is incresing counting efficiencies. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculated these minimum distances, and "ABS" seeks for the absolut values to the total sum of local distances. We have accomplished circuit design and verification about the "ADD" and "ABS" blocks, and performed total layout '||'&'||' DRC(design rule check) using 3um CMOS N-Well rule base.le check) using 3$\mu$m CMOS N-Well rule base.

• Proceedings of the Acoustical Society of Korea Conference
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• 1991.06a
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• pp.163-168
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• 1991

In this paper, we propose a new systolic architecture for the order statistics(OS) constant false alarm rate(CFAR) processor. In the proposed architecture, each processing element(PE) can compare two reference data cells with one test cell simultaneously in each clock cycle. So the utilization of each PE in this architecture is 100% whereas the utilization of each PE in the systolic architecture previously reported by Ritcey and Hwang is 50% because of one clock delay between two adjacent PE's active in computation. This can speed up the data processing rate by a factor of two. With this architecture, we can obtain the reduced number of communication links between adjacent PE's and reduction of the latency by half in comparison with the one proposed by Ritcey and Hwang.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.6
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• pp.1-9
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• 2010

In this paper, we propose a hi-speed/low-power Extended QRD-RLS(QR-Decomposition Recursive Least Squares) equalizer with systolic array structure. In the conventional systolic array structure, vector mode CORDIC on the boundary cell calculates angle of input vector, and the rotation mode CORDIC on the internal cell rotates vector. But, in the proposed structure, it is shown that implementation complexity can be reduced using the rotation direction of vector mode CORDIC and rotation mode CORDIC. Furthermore, calculation time can be reduced by 1/2 since vector mode and rotation mode CORDIC operate at the same time. Through HDL coding and chip implementation, it is shown that implementation area is reduced by 23.8% compared with one of conventional structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.40-47
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• 2006

The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.13-19
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• 2020

In this paper, we propose a multiplexer based scheme that performs modular AB² multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB² multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB² multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB² multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

• Journal of Korean Academy of Nursing
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• v.28 no.4
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• pp.980-991
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• 1998

The purpose of this study was to examnin the effect of slow stroke back massage(SSBM) on anxiety and immune response in patients undergoing open heart surgery and to compare the effect of 5-minutes with 10-minutes SSBM. Among the sixty-four patient subjects, twenty-one were one experimental group receiving massage for 10-minutes, twenty for the other experimental group receiving massage for 5-minutes and twenty-three for the control group. Subjects were admitted at Hospitals in Inchon and Puchon for open heart surgery. This study was carried out from October 10, 1997 to May 10, 1998. The levels of anxiety were measured by the Visual Analogue Scale(VAS), Trait anxiety scale, systolic and diastolic blood pressure, pulse rate, blood cortisol and the levels of immune response were measured by the blood T-lymphocyte and Natural killer cell. Study measurements were taken before and after SSBM on the 1st post operative day. Data were analyzed using x$^2$ test, oneway ANOVA, paired t-test, t-test and Pearson product moment correlation. The results were summarized as follows : 1. After SSBM, VAS anxiety level, systolic and diastolic blood pressure and pulse rate of the experimental group were decreased significantly than those measurements before the SSBM. After SSBM, significant difference in the VAS anxiety level, systolic blood pressure and pulse rate between the experimental and control groups were found. 2. After SSBM, the blood cortisol of the experimental and control groups were increased significantly compared with before SSBM. But the significant difference in blood cortisol between the two groups was not found. 3. After SSBM, the blood T-lymphocyte percentages of the experimental and control groups were decreased signigicantly and blood Natural killer cell percentages of the two groups were increased compared with before SSBM. But significant difference in blood T-lymphocyte and Natural killer cell percentages between the two groups was not found. 4. Significant difference in VAS anxiety level, systolic and diastolic blood pressure, pulse rate, blood cortisol, blood T-lymphocyte and Natural killer cell percentages between SSBM for 5 minutes and SSBM for 10 minutes were not found. Based upon the results, this study concludes that the slow stroke back massage for 5 minutes is a useful intervention that decreases anxiety and produces relaxation in patients undergoing open heart surgery.