• Title/Summary/Keyword: System-on-Chip Test

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An Analysis on the Thermal Shock Characteristics of Pb-free Solder Joints and UBM in Flip Chip Packages (플립칩 패키지에서 무연 솔더 조인트 및 UBM의 열충격 특성 해석)

  • Shin, Ki-Hoon;Kim, Hyoung-Tae;Jang, Dong-Young
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.16 no.5
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    • pp.134-139
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    • 2007
  • This paper presents a computer-based analysis on the thermal shock characteristics of Pb-free solder joints and UBM in flip chip assemblies. Among four types of popular UBM systems, TiW/Cu system with 95.5Sn-3.9Ag-0.6Cu solder joints was chosen for simulation. A simple 3D finite element model was first created only including silicon die, mixture between underfill and solder joints, and substrate. The displacements due to CTE mismatch between silicon die and substrate was then obtained through FE analysis. Finally, the obtained displacements were applied as mechanical loads to the whole 2D FE model and the characteristics of flip chip assemblies were analyzed. In addition, based on the hyperbolic sine law, the accumulated creep strain of Pb-free solder joints was calculated to predict the fatigue life of flip chip assemblies under thermal shock environments. The proposed method for fatigue life prediction will be evaluated through the cross check of the test results in the future work.

A Study on the Support Toning Method of High-Speed Chip-Mounter (고속 표면실장기의 지지부 개선 방법에 관한 연구)

  • Oh, Chang-Kyun;Park, Heung-Keun;Park, Jin-Moo
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2006.11a
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    • pp.597-602
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    • 2006
  • In this paper, a proper support tuning method is established by identifying the dynamic characteristics of the machine, the floor. and the inertia force. Also, the limitation of a passive isolation is presented. To simplify the dynamic analysis and to establish a proper design method for supporting system, each of the machine and the floor is modeled as a single degree of freedom spring-mass-damper system under careful investigation of the dynamic characteristics of each system and appropriate assumptions. Then, the dynamic behavior of a 2DOF system and the effect of the mass and the damping are investigated. Also, the characteristics of motion profiles are investigated. In addition, a quasi-static analysis on the transmitted force through support is performed and related tests are performed.

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Verification Study of Lifetime Prediction Models for Pb-Based and Pb-Free Solders Used in Chip Resistor Assemblies Under Thermal Cycling (온도변화 환경에서 칩저항 실장용 유·무연솔더의 수명모델 검증연구)

  • Han, Changwoon
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.40 no.3
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    • pp.259-265
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    • 2016
  • Recently, life prediction models for Pb-based and Pb-free solders used in chip resistor assemblies under thermal cycling have been introduced. The models suggest that the field lifetimes of Pb-free solders would be better than those of Pb-based solders when used for chip resistors under thermal cycling conditions, while the lifetime of the chip assemblies under accelerated test conditions show a reverse relationship. In this study, the prediction models were verified by applying the model to another research case. Finite element models were built, thermal cycling conditions were applied, and the energy densities were calculated. Finally, life prediction analysis was conducted for the cases where Pb-based and Pb-free solders were used. The prediction results were then compared with the test data of the case. It was verified that the predictions of the developed life cycle models are on the practical scale.

A Prediction-Based Dynamic Thermal Management Technique for Multi-Core Systems (멀티코어시스템에서의 예측 기반 동적 온도 관리 기법)

  • Kim, Won-Jin;Chung, Ki-Seok
    • IEMEK Journal of Embedded Systems and Applications
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    • v.4 no.2
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    • pp.55-62
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    • 2009
  • The power consumption of a high-end microprocessor increases very rapidly. High power consumption will lead to a rapid increase in the chip temperature as well. If the temperature reaches beyond a certain level, chip operation becomes either slow or unreliable. Therefore various approaches for Dynamic Thermal Management (DTM) have been proposed. In this paper, we propose a learning based temperature prediction scheme for a multi-core system. In this approach, from repeatedly executing an application, we learn the thermal patterns of the chip, and we control the temperature in advance through DTM. When the predicted temperature may go beyond a threshold value, we reduce the temperature by decreasing the operation frequencies of the corresponding core. We implement our temperature prediction on an Intel's Quad-Core system which has integrated digital thermal sensors. A Dynamic Frequency System (DFS) technique is implemented to have four frequency steps on a Linux kernel. We carried out experiments using Phoronix Test Suite benchmarks for Linux. The peak temperature has been reduced by on average $5^{\circ}C{\sim}7^{\circ}C$. The overall average temperature reduced from $72^{\circ}C$ to $65^{\circ}C$.

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An Efficient Test Access Mechanism for System On a Chip Testing (시스템 온 칩 테스트를 위한 효과적인 테스트 접근 구조)

  • Song, Dong-Seop;Bae, Sang-Min;Gang, Seong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.54-64
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    • 2002
  • Recently System On a Chip(SoC) design based on IP cores has become the trend of If design To prevent the testing problem from becoming the bottleneck of the core-based design, defining of an efficient test architecture and a successful test methodology are mandatory. This paper describes a test architecture and a test control access mechanism for SoC based on IEEE 1149.1 boundary,scan. The proposed SoC test architecture is fully compatible with IEEE P1500 Standard for Embedded Core Test(SECT), and applicable for both TAPed cores and Wrapped cores within a SOC with the same test access mechanism. Controlled by TCK, TMS, TDI, and TDO, the proposed test architecture provides a hierarchical test feature.

Accurate Extraction of Crosstalk Induced Dynamic Variation of Coupling Capacitance for Interconnect Lines of CMOSFETs

  • Kim, Yong-Goo;Ji, Hee-Hwan;Yoon, Hyung-Sun;Park, Sung-Hyung;Lee, Heui-Seung;Kang, Young-Seok;Kim, Dae-Byung;Kim, Dae-Mann;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.2
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    • pp.88-93
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    • 2004
  • We, for the first time, present novel test patterns and conclusive on-chip data indicating that the variation of coupling capacitance, ${\Delta}C_C$ by crosstalk can be larger than static coupling capacitance, $C_C$. The test chip is fabricated using a generic 150 nm CMOS technology with 7 level metallization. It is also shown that ${\Delta}C_C$ is strongly dependent on the phase of aggressive lines. For antiphase crosstalk ${\Delta}C_C$ is always larger than $C_C$ while for in-phase crosstalk $D_{\Delta}C_C$is smaller than $C_C$.

An Efficient Wrapper Design for SOC Testing (SOC 테스트를 위한 Wrapper 설계 기법)

  • Choi, Sun-Hwa;Kim, Moon-Joon;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.3
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    • pp.65-70
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    • 2004
  • The SOC(System on Chip) testing has required the core re-use methodology and the efficiency of test method because of increase of its cost. The goal of SOC testing is to minimize the testing time, area overhead, and power consumption during testing. Prior research has concentrated on only one aspect of the test core wrapper design problem at a test time. Our research is concentrated on optimization of test time and area overhead for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient wrapper design algorithm that improves on earlier approaches by also reducing the TAM(Test Access Mechanism) width required to achieve these lower testing times.

Reduced Pin Count Test Techniques using IEEE Std. 1149.7 (IEEE 1149.7 표준 테스트 인터페이스를 사용한 핀 수 절감 테스트 기술)

  • Lim, Myunghoon;Kim, Dooyoung;Mun, Changmin;Park, Sungju
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.9
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    • pp.60-67
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    • 2013
  • Test cost reduction is necessary to test a complex System-on-a-Chip(SoC) which adopts various Intellectual Properties (IP). In this paper, test architecture with low pin count which is able to IP-based SoC test, using IEEE Std. 1149.7 and IEEE Std. 1500, is proposed. IEEE Std. 1500 provides independent access mechanism for each IP in IP-based SoC test. In this paper, just two test pins are required by composing that these independent access mechanism can be controlled by IEEE Std. 1149.7. The number of Chips which are tested at the same time is increased by reducing required test pin count at wafer and package level test, and consequently the overall manufacturing test cost will be reduced significantly.

A Novel Test Scheduling Algorithm Considering Variations of Power Consumption in Embedded Cores of SoCs (시스템 온 칩(system-on-a-chip) 내부 코어들의 전력소모 변화를 고려한 새로운 테스트 스케쥴링 알고리듬 설계)

  • Lee, Jae-Min;Lee, Ho-Jin;Park, Jin-Sung
    • Journal of Digital Contents Society
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    • v.9 no.3
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    • pp.471-481
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    • 2008
  • Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

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A Study on the Charactistics of Machined Surface due to Cutter Runout (커터 런 아웃과 가공표면 생성에 관한 연구)

  • Hwang, J.;Lee, K. Y.;Shin, S. C.;Chung, E. S.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1997.04a
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    • pp.873-877
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    • 1997
  • This paper presents experimental results to know the charcteristics of machined surface due to cutter runout. Cutter runout is a common but undesirable phenomenon in multi-tooth machining such as end-milling process because it introduces variable chip loading to insert which results in a accelerated tool wear, amplification of force variation and hence enargement vibration amplitude. To develop in-proess cutter runout compensation system, set-up the micro-positoning mechanism which is based on piezoelectric translator embeded in the work holder to manipulate the depth of cut in real-time. And feasibility test of system was done under the various experimental cutting conditions. This results provide lots of information to build-up the precision machining technology.

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