• Title/Summary/Keyword: System-on-Chip Test

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Vibration Reduction of Chip-Mount System (칩 마운트 시스템의 진동 경감)

  • 임경화;장헌탁
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.11 no.8
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    • pp.331-337
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    • 2001
  • The purpose of this study is to analyze the principal causes of vibration problem and find out the method of vibration reduction in a chip-mount system. The principal causes are investigated through measurements of vibration spectrum and model parameters. Modal parameters are obtained by using an experimental model test. Based on the model parameters from experiments. a model of finite element method is formulated. The model presents effective redesign of increasing the natural frequencies in order to reduce the vibration of a chip-mount system. Further, through computer simulation for the behavior of head to be main vibration source, the best acceleration pattern of head movement can be verified to achieve effective head-positioning and reduce the vibration due to head movement.

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Design of Test Access Mechanism for AMBA based SoC (AMBA 기반 SoC 테스트를 위한 접근 메커니즘 설계)

  • Min, Pil-Jae;Song, Jae-Hoon;Yi, Hyun-Bean;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.74-79
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    • 2006
  • Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.

IEEE 1500 Wrapper and Test Control for Low-Cost SoC Test (저비용 SoC 테스트를 위한 IEEE 1500 래퍼 및 테스트 제어)

  • Yi, Hyun-Bean;Kim, Jin-Kyu;Jung, Tae-Jin;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.65-73
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    • 2007
  • This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.

A new efficient algorithm for test pattern compression considering low power test in SoC (SoC환경에서의 저전력 테스트를 고려한 테스트 패턴 압축에 대한 효율적인 알고리즘)

  • 신용승;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.85-95
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    • 2004
  • As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

A Study on Automated Bluetooth Communication Testing Methods Using CSR8670 Chip

  • Kim, Young-Mo;Noh, Hyun-Cheol;Kim, Seok-Yoon
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.5
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    • pp.65-71
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    • 2016
  • Bluetooth technology(BT) is a standard for short distance wireless communication and widely used to connect and control various electronic and telecommunication devices without wires, where CSR8670 chip is generally adopted. These BT devices are required to comply with BT specification and the equipments for conformance test are also important. However, the existing BT testing methods have inconvenience in that they are mostly time-consuming procedure due to not only repetitive execution for each evaluation element but also error-prone nature of manual experiments. This paper proposes an automated BT communication test method using CSR8670 chip, which solves the problems related to manual testing methods. The proposed method can reduce the development period of BT products and guarantee the quality improvement owing to the exact system error detection capability.

Development of a Test-Bed Autonomous Underwater Vehicle for Tank Test-Hardware and Software (자율 무인 잠수정(AUV)의 모의 실험을 위한 테스트베드의 개발-하드웨어와 소프트웨어)

  • 이판묵;전봉환;정성욱
    • Journal of Ocean Engineering and Technology
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    • v.11 no.1
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    • pp.106-112
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    • 1997
  • This paper describes the development of a test-bed vehicle named TAUV which can be a tool to evaluate the performance of a new control algorithm, operating software and the characteristics of sensors for an AUV. The test-bed AUV is designed to operate at depth of ten meters. It is 19.5kg in air and neural buoyancy in water and the dimension is $535{\times}400{\times}102mm$. TAUV is equipped with a magnetic compass, a biazial inclinometer, a rate gyro, a pressure sensor and an altitude sonae for measuring the motion of the vehicle. Two horizoltal thursters and two elevators are installed in order to propel and control the AUV. This paper persents the control system of TAUV which is based on a 16 bit single-chip microprocessor, 80c196kc, and the software architecture for the operating system. Experimental results are included to verify the performance of the TAUV.

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A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture

  • Han, Dongkwan;Lee, Yong;Kang, Sungho
    • ETRI Journal
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    • v.36 no.2
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    • pp.293-300
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    • 2014
  • As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

PERFORMANCE TEST OF THE KAO CCD IMAGING SYSTEM (천문대 극미광영상장비의 성능 시험)

  • JIN HO;HAN WONYONG;LEE SEOGU;LEE WOO-BAIK
    • Publications of The Korean Astronomical Society
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    • v.13 no.1 s.14
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    • pp.99-109
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    • 1998
  • Korea Astronomy Observatory (KAO) recently developed a new model of CCD imaging system for astronomical purpose. This paper presents system structure and electrical circuit descriptions with the performance of the CCD imaging system. The developed system can handle astronomical image acquisition with additional functions of on-chip binning, sub-image acquisition using a SITe $1024\times1024$ CCD chip. Particularly the controller design of the system allows us great flexibility and versatility with the software system control and it is possible to cope with any format CCDs by any manufactures, in principle. The system performances are derived by mean variance test in our laboratory, which shows that the total system noise 10.5e-(R.M.S), Gain 1.9e-/ ADD, non-linearity $0.37\%$

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Design and Implementation of FMCW Radar Based on two-chip for Autonomous Driving Sensor (자율주행센서로서 개발한 2-chip 기반의 FMCW MIMO 레이다 설계 및 구현)

  • Choi, Junhyeok;Park, Shinmyong;Lee, Changhyun;Baek, Seungyeol;Lee, Milim
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.6
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    • pp.43-49
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    • 2022
  • FMCW(Frequency Modulated Continuous Wave) Radar is very useful for vehicle collision warning system and autonomous driving sensor. In this paper, the design and implementation of FMCW radar based on two chip MMIC developed as an autonomous driving sensor was described. Especially, generation of frame-based and chirp-based waveform generation and signal processing are mixed to have the strength of maximum detection speed and compensation of speed. This implemented system was analyzed for performance and commercialization potential through lab. test and driving test in K-city.

Chip on Glass Interconnection using Lateral Thermosonic Bonding Technology (횡방향 열초음파 본딩 기법을 이용한 COG 접합)

  • Ha, Chang-Wan;Yun, Won-Soo;Park, Keum-Saeng;Kim, Kyung-Soo
    • Journal of the Korean Society for Precision Engineering
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    • v.27 no.7
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    • pp.7-12
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    • 2010
  • In this paper, chip-on-glass(COG) interconnection with anisotropic conductive film(ACF) using lateral thermosonic bonding technology is considered. In general, thermo-compression bonding which is used in practice for flip-chip bonding suffers from the low productivity due to the long bonding time. It will be shown that the bonding time can be improved by using lateral thermosonic bonding in which lateral ultrasonic vibration together with thermo-compression is utilized. By measuring the internal temperature of ACF, the fast curing of ACF thanks to lateral ultrasonic vibration will be verified. Moreover, to prove the reliability of the lateral thermosonic bonding, observation of pressured mark by conductive particles, shear test, and water absorption test will be conducted.