• Title/Summary/Keyword: System-on-Chip Test

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Efficient AMBA Based System-on-a-chip Core Test With IEEE 1500 Wrapper (IEEE 1500 래퍼를 이용한 효과적인 AMBA 기반 시스템-온-칩 코아 테스트)

  • Yi, Hyun-Bean;Han, Ju-Hee;Kim, Byeong-Jin;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.61-68
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    • 2008
  • This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

Development of Laser Diode Test Device using Feedback Control with Machine Vision (비젼 피드백 제어를 이용한 광통신 Laser Diode Test Device 개발)

  • 유철우;송문상;김재희;박상민;유범상
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2003.06a
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    • pp.1663-1667
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    • 2003
  • This thesis is on tile development of LD(Laser Diode) chip tester and the control system based on graphical programming language(LabVIEW) to control the equipment. The LD chip tester is used to test the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the receiver(optic fiber) are very small. Therefore, in order to test each chip precisely, this tester needs high accuracy. However each motion part of the tester could not accomplish hish accuracy due to the limit of the mechanical performance. Hence. an image processing with machine vision was carried out in order to compensate for the error. and also a load test was carried out so as to reduce tile impact of load on chip while the probing motion device is working. The obtained results were within ${\pm}$5$\mu\textrm{m}$ error.

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Power-aware Test Framework for NoC(Network-on-Chip) (NoC에서의 저전력 테스트 구조)

  • Jung, Jun-Mo;Ahn, Byung-Gyu
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.8 no.3
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    • pp.437-443
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    • 2007
  • In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

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Development and Characterization of Vertical Type Probe Card for High Density Probing Test (고밀도 프로빙 테스트를 위한 수직형 프로브카드의 제작 및 특성분석)

  • Min, Chul-Hong;Kim, Tae-Seon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.9
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    • pp.825-831
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    • 2006
  • As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

A Novel Built-In Self-Test Circuit for 5GHz Low Noise Amplifiers (5GHz 저잡음 증폭기를 위한 새로운 Built-In Self-Test 회로)

  • Ryu Jee-Youl;Noh Seok-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.5
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    • pp.1089-1095
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    • 2005
  • This paper presents a new low-cost Built-In Self-Test (BIST) circuit for 50Hz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SoC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gaih, noise figure, and input return loss all in a single SoC environment.

Low Power Scan Testing and Test Data Compression for System-On-a-Chip (System-On-a-Chip(SOC)에 대한 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트)

  • 정준모;정정화
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.12
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    • pp.1045-1054
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    • 2002
  • We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

Efficient Test Data Compression and Low Power Scan Testing for System-On-a-Chip(SOC) (SOC(System-On-a-Chip)에 있어서 효율적인 테스트 데이터 압축 및 저전력 스캔 테스트)

  • Park Byoung-Soo;Jung Jun-Mo
    • The Journal of the Korea Contents Association
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    • v.5 no.1
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    • pp.229-236
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    • 2005
  • Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

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Integration of SoC Test and Verification Using Embedded Processor and Reconfigurable Architecture (임베디드 프로세서와 재구성 가능한 구조를 이용한 SoC 테스트와 검증의 통합)

  • Kim Nam-Sub;Cho Won-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.7 s.349
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    • pp.38-49
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    • 2006
  • In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

Test Scheduling Algorithm of System-on-a-Chip Using Extended Tree Growing Graph (확장 나무성장 그래프를 이용한 시스템 온 칩의 테스트 스케줄링 알고리듬)

  • 박진성;이재민
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.3
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    • pp.93-100
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    • 2004
  • Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

  • Yi, Hyunbean
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.1
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    • pp.71-78
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    • 2013
  • In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.