• 제목/요약/키워드: System-on-Chip

검색결과 1,730건 처리시간 0.023초

선삭가공에 있어서 선삭저항의 신호처리와 그 응용에 관한 연구(II) (A Study on the Signal Process of Cutting Forces in Turning and its Application (2nd Report) -Automatic Monitor of Chip Rorms using Cutting Forces-)

  • 김도영;윤을재;남궁석
    • 한국정밀공학회지
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    • 제7권2호
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    • pp.85-94
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    • 1990
  • In automatic metal cuttings, the chip control is one of the serious problems. So the automatic detection of chip forms is essential to the chip control in automatic metal cuttings. Cutting experiments were carried out under the variety of cutting conditions (cutting speed, feed, depth of cut and tool geometry) and with workpiece made of steel (S45C), and cutting forces were measured in-processing by using a piezoelectric type Tool Dynamometer. In this report, the frequency analysis of dynamic components, the upper frequency distributions, the ratio of RMS values, the numbers of null point and the probability density were calculated from the dynamic componeents of cutting forces filtered through various band pass filters. Experimental results showed that computer chip form monitoring system based on the cutting forces was designed and simulated and that 6 type of chip forms could be detected while in-process machining.

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Biochemical Reactions on a Microfluidic Chip Based on a Precise Fluidic Handling Method at the Nanoliter Scale

  • Lee, Chang-Soo;Lee, Sang-Ho;Kim, Yun-Gon;Choi, Chang-Hyoung;Kim, Yong-Kweon;Kim, Byung-Gee
    • Biotechnology and Bioprocess Engineering:BBE
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    • 제11권2호
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    • pp.146-153
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    • 2006
  • A passive microfluidic delivery system using hydrophobic valving and pneumatic control was devised for microfluidic handling on a chip. The microfluidic metering, cutting, transport, and merging of two liquids on the chip were correctly performed. The error range of the accuracy of microfluid metering was below 4% on a 20 nL scale, which showed that microfluid was easily manipulated with the desired volume on a chip. For a study of the feasibility of biochemical reactions on the chip, a single enzymatic reaction, such as ${\beta}-galactosidase$ reaction, was performed. The detection limit of the substrate, i.e. fluorescein $di-{\beta}-galactopyranoside$ (FDG) of the ${\beta}-galactosidase$ (6.7 fM), was about 76 pM. Additionally, multiple biochemical reactions such as in vitro protein synthesis of enhanced green fluorescence protein (EGFP) were successfully demonstrated at the nanoliter scale, which suggests that our microfluidic chip can be applied not only to miniaturization of various biochemical reactions, but also to development of the microfluidic biochemical reaction system requiring a precise nano-scale control.

Chip Bonding Machine Base 구조해석에 관한 연구 (Study on the Structural Analysis of Chip Bonding Machine Base)

  • 김원종;황은하
    • 한국산업융합학회 논문집
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    • 제15권2호
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    • pp.55-58
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    • 2012
  • This study is concerned about the design and structural analysis of high integrated Chip Bonding Machine. Recently, many studies have been undergoing to reduce a working time in a field of Chip Bonding Machine. Chip Bonding Machine belongs to reduce a stand-by time by Chip Moving time. The developed system can save tool moving distance in small space than other machine. The analysis is carried out by SoldEdge & Ansys software.

차량용 반도체 공급망 생태계 (Supply Chain Ecosystem of Automotive Chip)

  • 전황수;김현탁;노태문
    • 전자통신동향분석
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    • 제36권3호
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    • pp.1-11
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    • 2021
  • In this study, we analyze the automotive chip ecosystem that recently caused the global supply shortage, and attempt to derive policy implications for us from the conclusion. Automotive chips are critical parts that control various systems so that a vehicle can drive itself or operate with electricity. The current shortage in supply and demand for automotive chips is due to the inconsistency between supply and demand between automotive chip companies and car manufacturers. To promote the automotive chip industry, new investment incentives, tax cuts, and human resource training are needed.

Multilayer thin Film technology as an Enabling technology for System-in-Package (SIP) and "Above-IC" Processing

  • Beyne, Eric
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2003년도 International Symposium
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    • pp.93-100
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    • 2003
  • The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

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Micro EDM을 이용한 Lab-on-a-chip금형의 미세 패턴 제작에 관한 연구 (A Study on the Micro Pattern Fabrication of Lab-on-a-chip Mold Master using Micro EDM)

  • 신봉철;김규복;조명우;김보현;정우철;허영무
    • 소성∙가공
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    • 제20권1호
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    • pp.17-22
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    • 2011
  • Recently, analyzing system is studying for applying to biomedical engineering field, actively. Micro fluidics control system has been manufactured using LIGA (Lithographie Galvanoformung und Abformung), Etching, Lithography and Laser etc. However, it is difficult that above-mentioned methods are applied to fabrication of precision mold master efficiently because of long processing time and rising cost of equipments. Therefore, in this study, micro EDM and micro WEDG system were developed to analyze machining characteristics with tool wear, surface roughness and process time. Then, optimal machining conditions could be obtained from the results of analysis. As the results, mold master of staggered herringbone mixer which has a high mixing efficiency, one of passive mixer of Lab-on-a-chip, could be fabricated from micro pattern(< 50um) using micro EDM successfully.

Network-on-Chip에서의 최적 통신구조 설계 (Optimal Design of Network-on-Chip Communication Sturcture)

  • 윤주형;황영시;정기석
    • 대한전자공학회논문지SD
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    • 제44권8호
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    • pp.80-88
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    • 2007
  • 매우 복잡한 시스템의 보다 효율적인 설계를 위한 차세대 SoC를 위해 중요한 것은 시스템의 고적용성과 고확장성이다. 이를 위해 최근 들어 급속히 관심이 높아지는 것이 계산 모듈중심의 시스템 설계를 탈피하여 통신 중심으로 시스템 설계를 보는 communication-based 설계 방법론이며, 그 중 대표적으로 많은 관심을 모으고 있는 것이 Network-on-Chip (NoC)이다. 이는 모듈간의 직접적인 연결에 의한 데이터의 통신 구조를 가진 일반적인 SoC 설계에서의 취약한 확장성과 통신 구조의 고정성을 극복하기 위해, 데이터를 패킷화하고, 이를 네트워크 인터페이스 및 라우터에 의한 가변적인 구조에 의해 전송함으로써 통신 구조의 적용성과 확장성을 제공하려는 노력이다. 하지만 확장성과 적용성에 치중하다 보면 성능과 면적에 대한 비용이 너무 커져서 실제로 기존의 연결 방법과 비교하여 실용성이 없을 수 있다. 그래서 본 연구에서는 통신 패턴의 면밀한 분석을 통하여 매우 성능에 중요하고 또 빈번한 통신 패턴에 대해서는 기존의 연결 방식을 고수하면서, 전체적인 연결성 및 확장성을 유지하는 알고리즘을 제시한다. 이 방법을 통해서 최소 30%의 네트워크 인터페이스 및 라우터 구조가 훨씬 간단한 구조로 바뀔 수 있었으며, 이로 인한 연결성 (connectivity) 및 확장성에 대한 손실은 거의 없었다. 시뮬레이션 결과에 의하면 통신 구조의 최적화를 통해서 연결에 소요되는 시간적 성능은 49.19% 향상되었고 면적의 측면에서도 24.03% 향상되었음이 입증되었다.

A New Automatic Compensation Network for System-on-Chip Transceivers

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • ETRI Journal
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    • 제29권3호
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    • pp.371-380
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    • 2007
  • This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 ${\mu}m$ SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.

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Development of DNA Chip System for Differential Diagnosis of Porcine Enteric Pathogens

  • Kim, Tae-ju;Cho, Ho-seong;Kim, Yong-hwan;A.W.M. Effendy;Park, Nam-yong
    • 한국수의병리학회:학술대회논문집
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    • 한국수의병리학회 2003년도 추계학술대회초록집
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    • pp.32-32
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    • 2003
  • Intestinal infections are common in growing pigs and can be caused by multiple pathogens, environmental and management factors [1]. Among the most important viruses in swine enteritis are porcine epidemic diarrhea virus (PEDV), transmissible gastroenteritis virus (TGEV), porcine enteric calicivirus (PECV), porcine group A rotavirus (PRV gp A) and bacteria are Escherichia coli and Salmonella spp. and protozoa is Isospora suis [1]. The DNA chip system can serve as a powerful tool that can be utilized for simultaneous detection of specific pathogenic bacteria strains and viruses [2,3]. The combination of PCR and DNA chip technology will provide a novel method for the detection of porcine enteric pathogens thus revolutionize the diagnosis and management of the disease. The aim of this study is to develop DNA chip system for the rapid and reliable detection of five major porcine enteric pathogens based on oligonucleotide DNA chip hybridization. (omitted)

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Easily Adaptable On-Chip Debug Architecture for Multicore Processors

  • Xu, Jing-Zhe;Park, Hyeongbae;Jung, Seungpyo;Park, Ju Sung
    • ETRI Journal
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    • 제35권2호
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    • pp.301-310
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    • 2013
  • Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.