• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.309-312
• /
• 2001

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.1272-1273
• /
• 2009

We demonstrate conformal phosphor coating and patterning methods on light emitting diodes (LEDs) using image processing based optofluidic maskless lithography (IP-OFML) system in microfluidic channels. IP-OFML allows a real-time detection and dynamic mask generation for packaging of randomly dispersed microchips. Our system detects each chip by considering rotation of the chip through image processing regardless of their arrangement error. Therefore, it precisely packages the chip making conformal polymer layer.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.40 no.2
• /
• pp.162-172
• /
• 1991

In proportion to the capacity enlargement of the induction motor system controlled by current source inverter, the capacitance of the commutating capacitor is enlarged and then the spike value of output voltage is increased at the moment of charge and discharge. Moreover, the output currnet includes a number of harmonic components. Such voltage spike and harmonics generate the torque ripple and lead to bad effects on the performance of the induction motor. In this study, all the harmonics excluding 17th and 19th harmonics were mostly elimunated by adopting 18-phase Triple High Frequency Current Source Inverter(HFCSI), and the spike component of output voltage was reduced by adding the Voltage Clamping Circuit(VCC). As a result, the torque ripple and the commutation loss were reduced and the performance of the system was improved. Experiments for speed control were carried out in the tripple current source inverter system for induction motor drive. Overall system was controlled by ONE CHIP MICROCOMPUTER(INTEL 8751). Control circuits were simplified and good experimental results in the constant V/F control were obtained due to the flexibility of the microcomputer.

• Journal of the Korea Convergence Society
• /
• v.10 no.11
• /
• pp.95-100
• /
• 2019

In this paper, autonomous vehicles of service with existing vehicle accident for the prevention of the vehicle communication technology, self-driving techniques, brakes automatic control technology, artificial intelligence technologies such as well and developed the vehicle accident this occur to death or has been techniques, can prepare various safety cases intended to minimize the injury. In this paper, it is a study to secure safety in autonomous vehicles. This is determined according to spatial factors such as chip signals for general low-power short-range wireless communication and micro road AI. On the other hand, in this paper, the safety of boarding is improved by checking the signal from the electronic chip, up to "recognition of the emotion from residence time in the sensing area" to the biological electronic chip. As a result of demonstrating the reliability of the world countries the world, inducing safety autonomous system of all passengers in terms of safety. Unmanned autonomous vehicle riding and commercialization will lead to AI systems and biochips (Verification), linked IoT on the road in the near future, and the safety technology reliability of the world will be highlighted.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.747-748
• /
• 2006

In this paper, we describe photonic sensor interface and driver program based on SOPC(System on a programmable chip) platform. This platform uses device that has ARM922T processor and APEX FPGA area on a chip. As for driver program development, three different methods are tried such as simple firmware, real-time OS based program and embedded Linux based program, and results are compared for SoC implementation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.2
• /
• pp.259-266
• /
• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• Journal of the Korea Society of Computer and Information
• /
• v.21 no.5
• /
• pp.65-71
• /
• 2016

Bluetooth technology(BT) is a standard for short distance wireless communication and widely used to connect and control various electronic and telecommunication devices without wires, where CSR8670 chip is generally adopted. These BT devices are required to comply with BT specification and the equipments for conformance test are also important. However, the existing BT testing methods have inconvenience in that they are mostly time-consuming procedure due to not only repetitive execution for each evaluation element but also error-prone nature of manual experiments. This paper proposes an automated BT communication test method using CSR8670 chip, which solves the problems related to manual testing methods. The proposed method can reduce the development period of BT products and guarantee the quality improvement owing to the exact system error detection capability.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.190-195
• /
• 2005

The hearing aid chip described in this paper is an analog & digital mixed system. The design focuses on the$\mu$DSP core. This $\mu$DSP core includes internal time delays to two inputs from front and rear microphones. The paper consists of two parts; one is the composure and signal processing algorithm of digital hearing aids and the other is Verilog HDL codes for$\mu$DSP cores. All digital modules in the design were coded and synthesized by Verilog HDL codes which were verified by Mentor Graphics and Synopsis semiconductor chip design tools.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.1
• /
• pp.34-41
• /
• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.6
• /
• pp.190-196
• /
• 1999

In this study, a procedure for analyzing chip-tool friction and shear processes in 3-D cutting with a single point tool has been established. The edge of a single point tool including circular nose is modified to the equivalent straight edge, then 3-D cutting with a single point tool is reduced to equivalent oblique cutting. Transforming the conventional coordinate systems and using the measured three component of cutting forces, force components on the rake face and the shear plane of the equivalent oblique cutting system can be obtained. And it can be possible to assess the chip-tool friction and shear characteristics in 3-D cutting with a single point tool.