• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.541-545
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• 2014

Rec. ITU-R M.1842-1 is international recommendation for VHF band communication guideline in maritime mobile service RR Appendix 18 channels. In this paper, we simulate 28.8 kbps VHF ${\pi}$/4-DQPSK digital baseband modem compatible with the recommendation, then it is designed and implemented with FPGA. Cazac sequence is used as a preamble since packet format is not defined untill now in the recommendation. Baseband modem is designed by VHDL language and implemented on NEXYS4 development platform having Atrix7 FPGA chip from Xilinx. For wireless communication test of total prototype system, ADC/DAC board is implemented and EV9730 RF module is utilized. From the experimental results, implemented FPGA modem shows spectral bandwidth of 25 kHz and successful data exchanges between tx and rx communication platform.

• Information and Communications Magazine
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• v.9 no.9
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• pp.72-85
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• 1992

The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

• Journal of Animal Environmental Science
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• v.19 no.2
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• pp.177-182
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• 2013

We studied the possibility to produce solid fuel using cattle manure and to apply TAO (Thermophilic Aerobic Oxidation) process of solid-liquid separation fraction. The physiochemical compositions of cattle manure solid fuel chip were analyzed as water 0.12%, low calorific value 3,510 kcal/kg, ashes 11.9%, chlorine 0.82%, sulfur dust 0.5%, mercury non-detection, cadmium 1.0 mg/kg, lead 2 mg/kg, arsenic non-detection. In treating cattle manure with TAO reactor the internal temperature of the reactor was increasing higher and $50^{\circ}C$ and over was maintained after 20 hours on. The physiochemical compositions of liquids increased from pH 7.3 to pH 9.18 and EC decreased from 4.6 to 3.48 mS/cm in treating process of cattle manure with TAO reactor. COD and SCOD decreased from 16,800 to 10,400 mg/L, from 4,600 to 2,040 mg/L respectively, which showed about 38% and 56% of remove efficiency respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.5
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• pp.2325-2331
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• 2012

Planar square-spiral antenna using a strip conductor is proposed and analyzed for RFID system in UHF band operating from 860MHz to 960MHz. By varying the length of common line, detached distance, strip line-space, strip line-width and the number of spiral turn, the optimized antenna are designed and fabricated in compact size without a matching-stub between the input port of the proposed antenna and RFID tag chip. From the optimized results, the frequency bandwidth in VSWR<2 has covered 100MHz in the RFID UHF band. The antenna gain has obtained 3.5dBi at the center frequency of 910MHz and the desired beam pattern has shown directional pattern on elevation and azimuth angle. Therefore, the proposed antenna is suitable for practical RFID applications requiring various tag chips with the specific input impedance.

• Journal of Digital Contents Society
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• v.5 no.4
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• pp.251-256
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• 2004

The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.77-83
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• 2004

In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.131-137
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• 2009

Binary offset carrier (BOC) signal synchronization is one of the most important steps to recover the transmitted information in global navigation satellite systems (GNSS) including Galileo and global positioning system (GPS). Generally, BOC signal synchronization is based on the correlation between the received and locally generated BOC signals. Thus, the multiple side-peaks in BOC autocorrelation are one of the main error sources in synchronizing BOC signals. Recently, a novel correlation function with reduced side-peaks was proposed for BOC signal synchronization by Julien [8]; however, Julien's correlation function not only still has the side-peaks, but also is only applicable to sine phased BOC(n, n), where n is the ratio of the pseudo random noise (PRN) code rate to 1.023 MHz. In this paper, we propose a new correlation function for BOC signal synchronization, which does not have any side-peaks and is applicable to general types of BOC signals, sine/cosine phased BOC(kn, n), where k is the ratio of a PRN chip duration to the period of a square wave sub-carrier used in BOC modulation. In addition, an efficient correlator structure is presented for generating the proposed correlation function.