• Biomolecules & Therapeutics
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• 제26권4호
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• pp.380-388
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• 2018

Neural stem cells (NSCs) have the ability to self-renew and differentiate into multiple nervous system cell types. During embryonic development, the concentrations of soluble biological molecules have a critical role in controlling cell proliferation, migration, differentiation and apoptosis. In an effort to find optimal culture conditions for the generation of desired cell types in vitro, we used a microfluidic chip-generated growth factor gradient system. In the current study, NSCs in the microfluidic device remained healthy during the entire period of cell culture, and proliferated and differentiated in response to the concentration gradient of growth factors (epithermal growth factor and basic fibroblast growth factor). We also showed that overexpression of ASCL1 in NSCs increased neuronal differentiation depending on the concentration gradient of growth factors generated in the microfluidic gradient chip. The microfluidic system allowed us to study concentration-dependent effects of growth factors within a single device, while a traditional system requires multiple independent cultures using fixed growth factor concentrations. Our study suggests that the microfluidic gradient-generating chip is a powerful tool for determining the optimal culture conditions.

• 전기학회논문지
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• 제58권7호
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• pp.1418-1423
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• 2009

This paper describes the design and implementation of a System-on-a-Chip (SoC) for image processing applications to use in wearable/mobile products. The target Soc consists of LEON 2 core, AMBA/APB bus-systems and custom-designed controllers. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, an image processing application is performed.

• 한국정보과학회논문지:시스템및이론
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• 제35권7호
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• pp.354-360
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• 2008

최신의 마이크로프로세서 설계에서는 전력 관련 문제들이 중요한 고려사항이 되었다. 온-칩(On-chip) 온도 상승은 이와 관련하여 중요한 요소로 부각되었다. 이를 적절하게 처리하지 않을 경우 냉각 비용과 칩 신뢰성에 부정적인 결과를 초래한다. 이 논문에서 우리는 시간적/공간적인 핫 스폿(Hot spot) 완화를 위한 설계들과 열 시간 상수, 작업부하 변동, 마이크로프로세서의 전력 분배 사이의 보편적인 상충관계(Trade off)들을 조사한다. 우리의 방안은 작업부하의 실행위치/순서를 변경하고 동시실행 스레드의 수를 조절하여 시스템의 공간 및 시간적인 열 틈새(Heat slack)에 영향을 줌으로써, 운영체계(OS)와 이미 시스템에 존재하는 하드웨어의 지원만으로 적절한 시간제한내에 작업부하를 조절함으로써 온-칩 온도를 낮출 수 있다.

• 전기전자학회논문지
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• 제23권1호
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• pp.295-301
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• 2019

바이오샘플의 DNA를 대량 증폭할 수 있는 휴대형 실시간 중합효소연쇄반응(Real-time PCR) 기기에서 히터는 PCR 반응 온도를 제어하기 위한 중요한 요소 중의 하나이다. 보통 빠른 히팅을 위해 소형 PCR 칩에 집적화되어 있고, 반도체 공정을 이용하여 박막형태로 제작되어 PCR 칩 제작 단가가 높은 편이다. 따라서 본 연구에서는 값싸고 온도제어를 정확히 할 수 있는 히터로 칩 저항을 사용하는 것을 제안한다. 칩 저항을 사용한 히터는 구조가 단순하고 제작이 쉽다는 장점이 있다. $2.54{\times}2.54cm^2$ 크기의 실시간 PCR 칩 위에 칩 저항을 1개 또는 2개를 사용했을 때 온도분포를 시뮬레이션 하였고, 고른 온도분포를 갖는 PCR 칩을 제작했다. 또한 효율적인 PCR 칩 냉각을 위해 소형 fan이 내장된 하우징을 설계하였고, 3D 프린터로 제작했다. 온도제어는 마이크로프로세서를 이용한 PID제어법(Proportional-Integral-Differential control)을 적용했다. 온도상승비와 하강비는 각각 $18^{\circ}C/s$, $3^{\circ}C/s$이며, 각 PCR 반응 단계의 유지 시간을 30초로 하였을 때, 한 사이클은 약 2.66분이 걸렸고, 35 사이클은 약 93 분 내로 진행할 수 있었다.

• ETRI Journal
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• 제22권4호
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• pp.13-24
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• 2000

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.

• ETRI Journal
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• 제32권4호
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• pp.540-547
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• 2010

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

• 한국정보통신학회논문지
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• 제26권10호
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• 한국정보통신학회논문지
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• 제26권11호
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• pp.1747-1750
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• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• 한국진공학회지
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• 제17권6호
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• pp.549-554
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• 2008

수소 플라즈마 처리된 유리 기판에 스핀 코팅 시스템을 이용하여 nickel chloride를 코팅하여 단백질칩 플레이트를 제조하였다. 다양한 플라즈마 처리 시간대에서 histidine tagged 단백질의 부착 능력 특성을 연구하였다. 유리 기판 표면에서 nickel chloride와 단백질 특성을 particle size analysis를 이용하여 관찰하였고, 단백질의 부착 능력 정도를 bio imaging analyzer system으로 측정하였다. 실험 결과에 따르면, 플라즈마 처리 시간이 증가할수록 단백질 부착 능력은 감소하는 것으로 나타났다. 기판 표면에서의 단백질 부착능력 특성에 관한 mechanism은 본문의 결과 및 토의에서 논의되었다. 플라즈마 처리된 단백질칩 기판에 대한 표면 안정화는 바이오센서 시장에서 큰 관심을 끌 것으로 기대된다.

• 전기학회논문지
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• 제56권8호
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• pp.1424-1429
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• 2007

This paper presents a simple and reliable one-touch type multi-immunosensing lab-on-a-chip (LOC) detecting antibodies as multi-disease markers using electrochemical method suitable for a portable point-of-care system (POCS). The multi-stacked LOC consists of a PDMS space layer for liquids loading, a PDMS valve layer with 50 im in height for the membrane, a PDMS channel layer for the fluid paths, and a glass layer for multi electrodes. For the disposable immunoassay which needs sequential flow control of sample and buffer liquids according to the designed strategies, reliable and easy-controlled on-chip operation mechanisms without any electric power are necessary. The driving forces of sequential liquids transfer are the capillary attraction force and the pneumatic pressure generated by air bladder push. These passive fluid transport mechanisms are suitable for single-use LOC module. Prior to the application of detection of the antibody as a disease marker, the model experiments were performed with anti-DNP antibody and anti-biotin antibody as target analytes. The flow test results demonstrate that we can control the fluid flow easily by using the capillary stop valve and the PDMS check valves. By the model tests, we confirmed that the proposed LOC is easily applicable to the bioanalytic immunosensors using bioelectrocatalysis.