• 전자공학회논문지B
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• 제33B권2호
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• 방사성폐기물학회지
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• 제19권4호
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• pp.469-477
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• 2021

Safe storage of spent nuclear fuel in deep underground repositories necessitates an understanding of the long-term alteration of metal canisters and buffer materials. A small-scale laboratory alteration test was performed on metal (Cu or Fe) chips embedded in compacted bentonite blocks placed in anaerobic water for 1 year. Lactate, sulfate, and bacteria were separately added to the water to promote biochemical reactions in the system. The bentonite blocks immersed in the water were dismantled after 1 year, showing that their alteration was insignificant. However, the Cu chip exhibited some microscopic etch pits on its surface, wherein a slight sulfur component was detected. Overall, the Fe chip was more corroded than the Cu chip under the same conditions. The secondary phase of the Fe chip was locally found as carbonate materials, such as siderite (FeCO₃) and calcite ((Ca, Fe)CO₃). These secondary products can imply that the local carbonate occurrence on the Fe chip may be initiated and developed by an evolution (alteration) of bentonite and a diffusive provision of biogenic CO₂ gas. These laboratory scale results suggest that the actual long-term alteration of metal canisters/bentonite blocks in the engineered barrier could be possible by microbial activities.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 춘계종합학술대회
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• pp.481-484
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• 2007

본 논문에서는 임베디드시스템에 기초를 둔 시스템온칩을 구성하는 방법을 제안하였다. 제안한 방법은 이전의 방법에 비해 좀 더 콤팩트하고 효과적이다. 이 방법은 높은 수행시뮬레이션을 요구하고 하드웨어/소프트웨어 통합설계 툴을 사용하여 구현을 위한 실행 가능한 규격화된 적절함을 요구한다. 시스템 인터페이스 처럼 이미 존재하고 있는 부품의 재사용은 지원되지만, 작업 이후는 단지 하드웨어/소프트웨어 통합설계 툴의 프로그램에 의해 수행되어진다. 실제 설계 흐름은 모든 프로세스를 통하여 요구되는 구현으로부터 모든 설계 단계 사이의 궤환을 허용하게끔 설명되어진다. 향후 좀더 진보된 임베디드시스템에 기초를 둔 시스템은칩을 구성하는 방법이 요구된다.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1996년도 춘계학술대회 논문집
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• pp.24-29
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• 1996

The seniconductor, which is precision product, requires many inspection processes. The surface conditions of the semiconductor chip effect on the functions of the semiconductors. The defects of the chip surface is crack or void. Because general inspection method requires many inspection processes, the inspection system which searches immediately and preciselythe defects of the semiconductor chip surface. We propose the inspection method by using the computer vision system. This study presents an image processing algorithm for inspecting the surface defects(crack, void)of the semiconductor test samples. The proposed image processing algorithm aims to reduce inspection time, and to analyze those experienced operator. This paper regards the chip surface as random texture, and deals with the image modeling of randon texture image for searching the surface defects. For texture modeling, we consider the relation of a pixel and neighborhood pixels as noncasul model and extract the statistical characteristics from the radom texture field by using the 2D AR model(Aut oregressive). This paper regards on image as the output of linear system, and considers the fidelity or intelligibility criteria for measuring the quality of an image or the performance of the processing techinque. This study utilizes the variance of prediction error which is computed by substituting the gary level of pixel of another texture field into the two dimensional AR(autoregressive model)model fitted to the texture field, estimate the parameter us-ing the PAA(parameter adaptation algorithm) and design the defect detection filter. Later, we next try to study the defect detection search algorithm.

• 한국정보과학회논문지:시스템및이론
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• 제32권9호
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• pp.465-474
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• 2005

고집적 SoC 설계시에 버스방식의 온칩 통신은 대역폭이 제한되는 문제점이 있고 NoC (Network-on-Chip) 방식에서는 구현의 복잡도가 증가하는 문제점이 있다. 본 논문에서는 이러한 문제점을 극복하는 새로운 온칩 통신 규격인 SNP(Soc Network Protocol)를 소개한다. SNP는 기존 버스의 신호선들을 세 가지 그룹인 제어(control), 주소(address), 데이타(data)로 나눈 뒤 하나의 채널을 통해 전송함으로써 신호선의 수를 줄인다. SNP 채널은 대칭구조로 사용되기 때문에 마스터-슬레이브 통신 방식뿐만 아니라 마스터-마스터 통신도 효율적으로 지원한다. 하나의 전송에 필요한 신호 그룹의 진행 규칙을 SNP 규격으로 정의하고, 동일한 정보가 반복적으로 전달되는 것을 방지하는 페이즈 복원 기능을 제안하여 통신대역을 효율적으로 사용할 수 있도록 한다. 산업계 표준 규격인 AMBA AHB와 비교한 결과 멀티미디어 타입의 데이타 전송시에 $54\%$의 신호선수만으로도 대등한 대역폭을 지원할 수 있음을 보인다.

• Journal of Information Processing Systems
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• 제3권1호
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• pp.16-20
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• 2007

This paper describes the development of the sensor interface and driver program for a point of care (POC) device. The proposed pac device comprises an ARM9 embedded processor and eight-channel sensor input to measure various bio-signals. It features a user-friendly interface using a full-color TFT-LCD and touch-screen, and a bluetooth wireless communication module. The proposed device is based on the system on a programmable chip (SOPC). We use Altera's Excalibur device, which has an ARM9 and FPGA area on a chip, as a test bed for the development of interface hardware and driver software.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 추계학술대회 논문집
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• pp.102-105
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• 2000

A simple digital control system has been developed for the frequency stabilization of an internal mirror He-Ne laser. The system is based on one chip microprocessor with embedded Basic interpreter. To stabilize the laser output frequency, the signal such as power difference or beat frequency between two modes is supplied and processed by a microprocessor, and control signal is fed to the heating coil would round the laser tube for adjusting the spacing of the laser cavity mirror. Newly developed frequency stabilization system is totally digitized. The system and the frequency stability performance are briefly described.

• TTA 저널
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• 통권93호
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• pp.88-95
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• 2004

• 대한전자공학회논문지SD
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• 제43권7호
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• pp.38-49
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• 2006

본 논문에서는 SoC를 검증 및 테스트하기 위한 새로운 개념의 칩을 제안하고 이를 SwToC(System with Test on a Chip)라 명명한다. SwToC는 SoC의 임베디드 프로세서에 재구성 가능한 로직을 추가하여 칩의 물리적인 결함을 테스트할 수 있을 뿐만 아니라 기존의 기법으로는 수행이 어려웠던 테스트 단계에서의 디자인 검증이 가능하도록 한 칩을 말한다. 제안한 개념의 칩은 고속 검증이 가능하며 테스트를 위해 많은 비용이 소모되는 ATE 가 불필요한 장점을 갖고 있다. 제안한 칩의 디자인 검증 및 테스트 기능을 평가하기 위하여 임베디드 프로세서가 내장된 상용 FPGA를 이용하여 SwToC를 구현하였으며, 구현 결과 제안한 칩의 실현 가능성을 확인하였고 적은 비용의 단말기를 통한 테스트가 가능함은 물론 기존의 검증기법에 비해 고속 검증이 가능함을 확인하였다.

• ETRI Journal
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• 제19권3호
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.