• Title/Summary/Keyword: System semiconductor

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Macro Modeling and Parameter Extraction of Lateral Double Diffused Metal Oxide Semiconductor Transistor

  • Kim, Sang-Yong;Kim, Il-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.12 no.1
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    • pp.7-10
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    • 2011
  • High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

Smart contract-based Business Model for growth of Korea Fabless System Semiconductor (한국 팹리스 시스템 반도체 발전을 위한 스마트계약 기반 거래 모델)

  • Hyoung-woo Kim;Seng-phil Hong;Majer, Marko
    • Journal of Advanced Navigation Technology
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    • v.27 no.2
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    • pp.235-246
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    • 2023
  • In the rapid technological development of artificial intelligence (AI), electric vehicles, and robots based the fourth industrial revolution, semiconductors determine the core performance, and semiconductor competitiveness is directly related to national competitiveness. However, the Korean semiconductor industry has continuously weakened its competitiveness in the system semiconductor field, excluding memory semiconductors, so in this study, a new smart contract basedblockchain business model to engage the global market, which is the most urgent need for the growth of Korean fabless system semiconductor industry in recession. F-SBM (Fabless-Smart contract based Blockchain Model) proposed. In this study, through the new F-SBM, it was verified how to engage new customers for fabless firms through smart contract based consortium blockchain regarding technology, economy, and reliability items of fabless. This model has great significance in improving the high entry barriers to engaging new customers for the long-cherished desire of the Korean fabless system semiconductor industry and deriving new growth solutions.

TV Automatic Control System for Single-person Households (1인 가구를 위한 TV자동 제어 시스템)

  • Kim, Eun Seo;Lim, Jaeyun;Kim, Sunhee
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.1
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    • pp.44-49
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    • 2022
  • The number of single-person households is increasing worldwide, and among them, the proportion of elderly single-person households is increasing. In the case of elderly single-person households, a significant portion of their leisure time is devoted to watching TV. However, if they fall asleep while watching TV without turning it off, it may be difficult to sleep well due to lights and sounds of TV, which can cause health problems such as depression and reduced immunity. Therefore, in this paper, we propose a system that automatically turns off the TV when a person watching TV falls asleep. Images are collected using the camera installed in front of the TV. Since the posture of a person watching TV varies from a sitting posture to a lying posture, the system is designed to determine whether or not to fall asleep regardless of the posture. In addition, since it becomes difficult to judge eye movements as a person moves away from the TV, a method for extending the judgmentable distance is proposed. The system model was implemented and tested using a Raspberry Pi, a monitor, an infrared sensor, and a camera. Eye movements were judged regardless of sitting or lying position, and the distance between a user and a TV was extended by about 200 cm.

Construction of Knowledge Base for Fault Tracking Expert System in Semiconductor Production Line (반도체 생산 라인에서의 이탈 처리 추적 전문가 시스템의 지식베이스 구축)

  • 김형종;조대호;이칠기;김훈모;노용한
    • Journal of Institute of Control, Robotics and Systems
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    • v.5 no.1
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    • pp.54-61
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    • 1999
  • Objective of the research is to put the vast and complex fault tracking knowledge of human experts in semiconductor production line into the knowledge base of computer system. We mined the fault tracking knowledge of domain experts(engineers of production line) for the construction of knowledge base of the expert system. Object oriented fact models which increase the extensibility and reusability have been built. The rules are designed to perform the fault diagnosis of the items in production device. We have exploited the evidence accumulation method to assign check priority in rules. The major contribution is in the overall design and implementation of the nile base and related facts of the expert system in object oriented paradigm for the application of the system in fault diagnosis in semiconductor production line.

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Implementation of Monitoring and Control System for Fire Engine Pump using the AJAX (AJAX를 이용한 소방엔진펌프의 모니터링과 제어 시스템 구현)

  • Yang, Oh;Lee, Heon-Guk
    • Journal of the Semiconductor & Display Technology
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    • v.15 no.3
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    • pp.40-45
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    • 2016
  • In this paper, the fire engine pump is controlled and monitored by the AJAX (Asynchronous Javascript and Xml) in the web server. The embedded system with built-in system having a processor and a memory of high performance occurs many problems in transmitting the large amount of data in real time through the web server. The AJAX is different from HTML (Hyper Text Makeup Language) with java script technology and can make RIA (Rich Internet Application). It process the necessary data by using asynchronous and it take advantage of usefulness, accessibility, a fast response time. Using AJAX can build up web server with real time and monitoring that fire engine pump status, check processing pump memory in the event of fire, also remotely monitors can do. The web server system can control the fire engine pump as like the black box. The experimental results show the effectiveness and commercialize possibility.

Design and Implementation of a Six-Stage Pipeline RV32I Processor Based on RISC-V Architecture (RISC-V 아키텍처 기반 6단계 파이프라인 RV32I프로세서의 설계 및 구현)

  • Kyoungjin Min;Seojin Choi;Yubeen Hwang;Sunhee Kim
    • Journal of the Semiconductor & Display Technology
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    • v.23 no.2
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    • pp.76-81
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    • 2024
  • UC Berkeley developed RISC-V, which is an open-source Instruction Set Architecture. This paper proposes a 32-bit 6-stage pipeline architecture based on the RV32I RSIC-V. The performance of the proposed 6-stage pipeline architecture is compared with the existing 32-bit 5-stage pipeline architecture also based on the RV32I processor ISA to determine the impact of the number of pipeline stages on performance. The RISC-V processor is designed in Verilog-HDL and implemented using Quartus Prime 20.1. To compare performance the Dhrystone benchmark is used. Subsequently, peripherals such as GPIO, TIMER, and UART are connected to verify operation through an FPGA. The maximum clock frequency for the 5-stage pipeline processor is 42.02 MHz, while for the 6-stage pipeline processor, it was 49.9MHz, representing an 18.75% increase.

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A Study of Semiconductor Process Control using Dual Damping EWMA (Dual Damping EWMA를 이용한 효율적인 반도체 공정 제어에 관한 연구)

  • Kim, Seon-Eok;Ko, Hyo-Heon;Kim, Jih-Yun;Kim, Sung-Shick
    • IE interfaces
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    • v.21 no.2
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    • pp.141-150
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    • 2008
  • In this paper, an efficient control method for semiconductor fabrication process is presented. Generally, control is performed with data which is under the influence of process disturbance. EWMA is one of the most popular control methods in semiconductor fabrication that effectively deals with varying process condition. A new method using EWMA, called the Dual Damping EWMA, is presented in this study to reduce over-control by separating weight factor of input and output. The goal is to reflect Drift but reduce the effects of White noise in run to run control. Simulation is performed to evaluate the performance of DPEWMA and to compare with EWMA and Double EWMA.

Development of Hard Mask Strip Inspection System for Semiconductor Wafer Manufacturing Process (반도체 전공정의 하드마스크 스트립 검사시스템 개발)

  • Lee, Jonghwan;Jung, Seong Wook;Kim, Min Je
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.3
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    • pp.55-60
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    • 2020
  • The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

Electrical properties and thermal stability of Al/$WN_x$/Ti submicron contact structure

  • Kim, Yong-Tae;Sim, Hyun-Sang;Kim, Seong-Il
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2002.11a
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    • pp.72-74
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    • 2002
  • A submicron contact scheme using $WN_x$ diffusion barrier has been suggested for multilevel interconnect structure. The contact resistance of $0.4\times0.48\mu\textrm{m}^2$ size Al/WN/Ti/$n^+$-Si is 120-140 $\Omega$ and the leakage current density is below than $10^{-16}$$-10^{-15}A/\mu\textrm{m}^2$. The effect of F atoms on the submicron contact has been investigated with the nuclear resonance analysis method.

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Compact Modeling for Nanosheet FET Based on TCAD-Machine Learning (TCAD-머신러닝 기반 나노시트 FETs 컴팩트 모델링)

  • Junhyeok Song;Wonbok Lee;Jonghwan Lee
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.4
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    • pp.136-141
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    • 2023
  • The continuous shrinking of transistors in integrated circuits leads to difficulties in improving performance, resulting in the emerging transistors such as nanosheet field-effect transistors. In this paper, we propose a TCAD-machine learning framework of nanosheet FETs to model the current-voltage characteristics. Sentaurus TCAD simulations of nanosheet FETs are performed to obtain a large amount of device data. A machine learning model of I-V characteristics is trained using the multi-layer perceptron from these TCAD data. The weights and biases obtained from multi-layer perceptron are implemented in a PSPICE netlist to verify the accuracy of I-V and the DC transfer characteristics of a CMOS inverter. It is found that the proposed machine learning model is applicable to the prediction of nanosheet field-effect transistors device and circuit performance.

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