• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1509-1514
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• 2011

The core of IT products, electronic components, especially the MLCC, chip inductors, chip Varistors and so on. In order to test the electrical characteristics of the chip using the Reno-pin contact test method has been used. In current chips, mass production of semiconductor manufacturing processes, high-speed production test for the chip speed up, precision is required. But Vibration displacement is a very short, so in order to overcome these shortcomings, the displacement amplification to design the structure has been actively studied. In this paper, a building structure with a flexible hinge was designed amplification instrument, semiconductor chip industry in the performance test and inspection equipment to measure the electrical characteristics of high speed linear actuators Reno-Pin using system was developed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.8
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• pp.1424-1429
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• 2007

This paper presents a simple and reliable one-touch type multi-immunosensing lab-on-a-chip (LOC) detecting antibodies as multi-disease markers using electrochemical method suitable for a portable point-of-care system (POCS). The multi-stacked LOC consists of a PDMS space layer for liquids loading, a PDMS valve layer with 50 im in height for the membrane, a PDMS channel layer for the fluid paths, and a glass layer for multi electrodes. For the disposable immunoassay which needs sequential flow control of sample and buffer liquids according to the designed strategies, reliable and easy-controlled on-chip operation mechanisms without any electric power are necessary. The driving forces of sequential liquids transfer are the capillary attraction force and the pneumatic pressure generated by air bladder push. These passive fluid transport mechanisms are suitable for single-use LOC module. Prior to the application of detection of the antibody as a disease marker, the model experiments were performed with anti-DNP antibody and anti-biotin antibody as target analytes. The flow test results demonstrate that we can control the fluid flow easily by using the capillary stop valve and the PDMS check valves. By the model tests, we confirmed that the proposed LOC is easily applicable to the bioanalytic immunosensors using bioelectrocatalysis.

• International Journal of Control, Automation, and Systems
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• v.4 no.5
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• pp.567-574
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• 2006

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate array (FPGA) chip has been developed to complete hardware implementation of a neural controller. The developed neural control hardware has been tested for balancing the inverted pendulum while controlling a desired trajectory of a cart as a nonlinear system.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Biomolecules & Therapeutics
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• v.26 no.4
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• pp.380-388
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• 2018

Neural stem cells (NSCs) have the ability to self-renew and differentiate into multiple nervous system cell types. During embryonic development, the concentrations of soluble biological molecules have a critical role in controlling cell proliferation, migration, differentiation and apoptosis. In an effort to find optimal culture conditions for the generation of desired cell types in vitro, we used a microfluidic chip-generated growth factor gradient system. In the current study, NSCs in the microfluidic device remained healthy during the entire period of cell culture, and proliferated and differentiated in response to the concentration gradient of growth factors (epithermal growth factor and basic fibroblast growth factor). We also showed that overexpression of ASCL1 in NSCs increased neuronal differentiation depending on the concentration gradient of growth factors generated in the microfluidic gradient chip. The microfluidic system allowed us to study concentration-dependent effects of growth factors within a single device, while a traditional system requires multiple independent cultures using fixed growth factor concentrations. Our study suggests that the microfluidic gradient-generating chip is a powerful tool for determining the optimal culture conditions.

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.1-11
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• 2021

In this study, we analyze the automotive chip ecosystem that recently caused the global supply shortage, and attempt to derive policy implications for us from the conclusion. Automotive chips are critical parts that control various systems so that a vehicle can drive itself or operate with electricity. The current shortage in supply and demand for automotive chips is due to the inconsistency between supply and demand between automotive chip companies and car manufacturers. To promote the automotive chip industry, new investment incentives, tax cuts, and human resource training are needed.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.3
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• pp.261-266
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• 2004

Recently, a variety of intelligent robots are developed for the personal purpose beyond the industrial application. These intelligent robots have ranges of sensors, actuators, and control algorithms to their application. In this paper we propose a reconfigurable robot controller, $SR^2$c (The SOPC-based Reconfigurable Robot Controller), based on SOPC (System on a Programmable Chip), that can be reconfigurable easily by software. The proposed robot controller contains not only a processing module but also robot-specific IP's. To show a feasibility of the proposed robot controller, a small entertainment robot, Wizard-4 is implemented with a single chip controller as proposed in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.38-49
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• 2006

In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.