• 한국통신학회논문지
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• 제40권3호
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• pp.559-567
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• 2015

This paper focuses on evaluating the performance of a cellular network using power control based frequency reuse partitioning (FRP) in downlink (DL). In our work, in order to have the realistic environment, the spectral efficiency of the system is evaluated through traffic analysis, which most of the previous works did not consider. To further decrease the cell edge user's outage, the concept of power ratio is introduced and applied to the DL FRP based cellular network. In considering network topology, we first divide the cell coverage area into two regions, the inner and outer regions. We then allocate different sub-bands in the inner and outer regions of each cell. In the analysis, for each zone ratio, the performance of FRP system is evaluated for the given number of power ratios. We consider performance metrics such as call blocking probability, channel utilization, outage probability and effective throughput. The simulation results show that there is a significant improvement in the outage experienced by outer UEs with power control scheme compared to that with no power control scheme and an increase in overall system throughput.

• 전기학회논문지
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• 제57권4호
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• pp.692-699
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• 2008

Semiconductor research and development(R&D) fabs are very different than production fabs in many ways such as the scales of production, job priority, production methods, and performance measures. Efficient operations of R&D fabs are very important to the development of new product, process stability, high yield, and ultimately company competitiveness. This paper proposes the fab-wide scheduling method for operational optimization of the R&D fabs. Most scheduling systems of semiconductor fabs have only focused on maximizing throughput of each separated areas without considering WIP(works in process) flows of entire fab. In this paper, we proposes the a fab-wide scheduling system which schedules all lots to entire fab equipment at once. We develop the MIP(mixed integer programing) model which allocates the lots to production equipment considering many constraints of all processes and the CP(constraint programming) model which determines the sequences of the lots in the production equipment. The proposed FAB-wide scheduling model is applied to the newly constructed R&D fab. As a result, we have accomplished the system based automated job reservation, decrease of the hot lot delay, increase of the queue time satisfaction, the high throughput by maximizing the batch sizes, decrease of the WIP TAT(Turn Around Time).

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2003년도 봄 학술발표논문집 Vol.30 No.1 (C)
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• pp.515-517
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• 2003

In this paper we examine the effects of the required portions of guard timing spaces in a MAC frame of ETSI BRAN HIPERLAN/2 system such as inter-mobile guard timing space in UL(Up Link) duration, inter-RCH(Random CHannel) guard timing space, sector switch guard timing space. In particular, we calculate the number of OFDM(Orthogonal Frequency Division Multiplexing) symbols required for these guard timing spaces in a MAC frame. We them evaluate the throughput of HIPERLAN/2 system as we vary parameter such as the guard time values defined in [2], the number of DLCCs(Data Link Control Connections), and the number of RCHs. Finally we show by numerical results that the portions for the 새심 summation of required guard timing spaces in a MAC frame are not negligible, and that they should be properly considered when trying to evaluate the performance of MAC protocol of HIPERLAN/2 system and also when determining the number of RCHs as well as the number of DLCCs in UL PDU trains at an AP/CC(Access Point/Central Controller).

• ETRI Journal
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• 제44권3호
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• pp.450-461
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• 2022

The Gen-Z protocol is a memory semantic protocol between the memory and CPU used in computer architectures with large memory pools. This study presents the implementation of the Gen-Z hardware system configured using Gen-Z specification 1.0 and reports its performance. A hardware prototype of a DDR4 Gen-Z memory pool with an optimized character, a block device driver, and a file system for the Gen-Z hardware was designed. The Gen-Z IP was targeted to the FPGA, and a 512 GB Gen-Z memory pool was configured on an ×86 server. In the experiments, the latency and throughput of the Gen-Z memory were measured and compared with those of the local memory, SATA SSD, and NVMe using character or block device interfaces. The Gen-Z hardware exhibited superior throughput and latency performance compared with SATA SSD and NVMe at block sizes under 4 kB. The MySQL and File IO benchmark of Gen-Z showed good write performance in all block sizes and threads. Besides, it showed low latency in RocksDB's fillseq dbbench using the ext4 direct access filesystem.

• 분석과학
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• 제35권5호
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• pp.218-227
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• 2022

A simple and fast throughput flow injection (FI) system with a merging-zone technique was designed to determine ferrous and ferric in an aqueous solution. The method is based on the direct reaction of ferrous with a Bathophenanthroline reagent (Bphen) in acidic media. The forming red complex absorbs light at 533 nm. All conditions of the flow injection system were investigated. The analytical curve of ferrous was linear in the range of 0.07 to 4 mg/L with an r² value of 0.9968. The detection and quantification limits were 0.02 and 0.04 mg/L, respectively. The molar absorptivity and Sandell's sensitivity were 4.0577 × 10⁶ L/mol cm and 25 × 10^-5 ㎍/cm², respectively. The homemade valve was low-cost with high repeatability (n = 7) at an RSD of 1.26 % and zero dead volume. The values of the dispersion coefficient were 2.318, 2.022, and 1.636 for the concentrations of 0.2, 1, and 3 mg/L, respectively. The analysis throughput of the designed flow injection unit was 57 sample per hour.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.145-148
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• 2002

In a network communication process, cryptographic algorithms play important role for secure process. This paper presents a new system architecture named "DCCS." This system can handle flexible operations of both cryptographic algorithms and the keys. For experimental evaluation, two representative cryptographic algorithms DES and Triple-DES are designed and implemented into an FPGA chip on the SEBSW-1. Then the developed board is confirmed to change its cryptographic algorithms dynamically. Also its throughput confirmed the ability of the real-time net-work use of the designed system.

• 산업경영시스템학회지
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• 제14권24호
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• pp.97-103
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• 1991

This paper deals with a scheduling problem with the objective of maximizing the throughput rate in flexible manufacturing system with shop type. Manufacturing system is consisted of multi-stage in series. All kinds of parts are processed in same in processing time. No buffer space is allowed between stages, and no part waiting is allowed in each stage. Part flow control method for determining the optimal production sequence of all parts and the production starting time of each part is proposed.

• 공학논문집
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• 제2권1호
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• pp.39-47
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• 1997

실시간 2차원 디지털 IIR 필터링 알고리즘의 구현을 가능하게 하는 디지털 신호처리시스템의 효율적인 구조를 제안하였다. 제안된 구조는 시스템 레벨과 프로세서 레벨에서의 병렬처리를 통하여 높은 시스템 성능을 가능하게 하였다. 프로세서간의 데이터 통신의 양을 크게 줄였으며 시스템이 초기화된 이후에는 다른 오버헤드 없이 계산을 수행할 수 있도록 설계하여 전체 시스템의 효율을 극대화하였다. 기능 레벨의 시뮬레이션을 수행하였으며, 그 결과 1 사이클당 1개의 데이터를 처리할 수 있음을 확인하였다. 이는 단지 10MHz의 시스템 클럭을 사용하는 경우 2차원 4차 IIR필터를 실시간 비디오데이터에 적용할 수 있음을 의미하며, 시스템 클럭의 주파수를 올릴 경우 고선명 TV (HDTV) 등의 전후 처리 필터로 사용가능 할 것이다.

• 산업경영시스템학회지
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• 제42권1호
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• pp.55-63
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• 2019

This paper develops an algorithm to determine the batch size of the batch process in real time for improving production and efficient control of production system with multiple processes and batch processes. It is so important to find the batch size of the batch process, because the variability arising from the batch process in the production system affects the capacity of the production. Specifically, batch size could change system efficiency such as throughput, WIP (Work In Process) in production system, batch formation time and so on. In order to improve the system variability and productivity, real time batch size determined by considering the preparation time and batch formation time according to the number of operation of the batch process. The purpose of the study is to control the WIP by applying CONWIP production system method in the production line and implements an algorithm for a real time batch size decision in a batch process that requires long work preparation time and affects system efficiency. In order to verify the efficiency of the developed algorithm that determine the batch size in a real time, an existed production system with fixed the batch size will be implemented first and determines that batch size in real time considering WIP in queue and average lead time in the current system. To comparing the efficiency of a system with a fixed batch size and a system that determines a batch size in real time, the results are analyzed using three evaluation indexes of lead time, throughput, and average WIP of the queue.

• 한국정보과학회논문지:시스템및이론
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• 제30권5_6호
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• pp.299-306
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• 2003

본 논문에서는 내장형 실시간 시스템의 성능 개선을 위한 리엔지니어링(performance re-engineering) 기법을 제시한다. 시스템 리엔지니어링은 구현이 완료된 시스템에서 새로운 성능 요구사항을 만족시키기 위한 일련의 작업이라 할 수 있다. 일반적으로 실시간 시스템의 성능은 실시간 처리량(real-time throughput)과 입출력 시간 지연(input-to-output latency) 등으로 기술할 수 있으며 새로운 성능 요구사항은 이와 같은 파라미터를 통해 기술된다. 본 연구의 리엔지니어링 기법은 두 단계로 구성된다. 첫째, 시스템을 프로세스 네트워크의 형태로 파악한 후, 프로세스의 수행시간을 분석하여 병목(bottleneck)이 되는 프로세스를 찾아낸다. 둘째, 병목 프로세스의 수행시간을 개선한 수 있도록 프로세싱 요소의 성능비례계수(performance scaling factor)를 구한다. 성능비례계수는 성능 개선을 비율로 나타낸 것으로서 리엔지니어링 비용을 최소화하도록 그 값을 구한다. 따라서 유도된 성능비례계수에 따라 하드웨어 장치를 업그레이드하면 하드웨어 비용을 최적화할 수 있다. 이러한 방법을 사용하면 소프트웨어를 수정할 필요가 없으며, 리엔지니어링 비용 및 시간을 단축할 수 있다.