• 제목/요약/키워드: Synthesis Algorithm

검색결과 668건 처리시간 0.031초

FM 방식을 이용한 가야금 음의 합성에 관한 연구 (A Study of Synthesizing the Sound of Gayageum with FM Algorithm)

  • 김재용;권민도;장호근;우종식;박주성
    • 한국음향학회지
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    • 제16권3호
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    • pp.5-12
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    • 1997
  • 본 논문에서는 가야금 음의 분석결과를 바탕으로 가야금 음의 합성에 적합한 3 오퍼레이터 FM 합성방식을 고안하였다. 고안된 알고리즘에 사용될 파라메터를 MATLAB을 이용하여 추출하여 C언어를 이용하여 음을 합성하였다. 합성된 음을 주관적인 방법과 객관적인 방법으로 비교한 결과 두 음이 아주 흡사함을 확인했다. 제안된 합성방식을 DSP를 이용하여 구현하여 만든 합성음도 원음과 비슷한 음질을 가지는 것을 확인했다.

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레지스터 전송 수준에서의 VHDL 순서문 합성에 관한 연구 (A Study on Synthesis of VHDL Sequential Statements at Register Transfer Level)

  • 현민호;황선영
    • 전자공학회논문지A
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    • 제31A권5호
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    • pp.149-157
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    • 1994
  • This paper Presents an algorithm for synthesis of sequential statements described at RT level VHDL. The proposed algorithm transforms sequential statements in VHDL into data-flow description consisting of concurrent statements by local and global dependency analysis and output dependency elimination. Transformation into concurrent statements makes it possible to reduce the cost of the synthesized hardwares, thus to get optimal synthesis results that will befit the designer 's intention. This algorithm has been implemented on VSYN and experimental results show that more compact gate-level hardwares are generated compared with Power View system from ViewLogic and Design Analyzer from Synopsys.

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NETLA를 이용한 이진 신경회로망의 최적합성 (Optimal Synthesis of Binary Neural Network using NETLA)

  • 정종원;성상규;지석준;최우진;이준탁
    • 한국마린엔지니어링학회:학술대회논문집
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    • 한국마린엔지니어링학회 2002년도 춘계학술대회논문집
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    • pp.273-277
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    • 2002
  • This paper describes an optimal synthesis method of binary neural network(BNN) for an approximation problem of a circular region and synthetic image having four class using a newly proposed learning algorithm. Our object is to minimize the number of connections and neurons in hidden layer by using a Newly Expanded and Truncated Learning Algorithm(NETLA) based on the multilayer BNN. The synthesis method in the NETLA is based on the extension principle of Expanded and Truncated Learning (ETL) learning algorithm using the multilayer perceptron and is based on Expanded Sum of Product (ESP) as one of the boolean expression techniques. The number of the required neurons in hidden layer can be reduced and fasted for learning pattern recognition.. The superiority of this NETLA to other algorithms was proved by simulation.

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Estimation of Theoretical Yield for Ethanol Production from D-Xylose by Recombinant Saccharomyces cerevisiae Using Metabolic Pathway Synthesis Algorithm

  • Lee, Tae-Hee;Kim, Min-Young;Ryu, Yeon-Woo;Seo, Jin-Ho
    • Journal of Microbiology and Biotechnology
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    • 제11권3호
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    • pp.384-388
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    • 2001
  • The metabolic pathway synthesis algorithm was applied to estimate the maximum ethanol yield from xylose in a model recombinant Saccharomyces cerevisiae strain containing the genes involved in xylose metabolism. The stoichiometrically independent pathways were identified by constructing a biochemical reaction network for conversion of xylose to ethanol in the recombinant S. cerevisiae. Two independent pathways were obtained in xylose-assimilating recombinant S. cerevisiae as opposed to six independent pathways for conversion of glucose to ethanol. The maximum ethanol yield from xylose was estimated to be 0.46 g/g, which was lower than the known value of 0.51 g/g for glucose-fermenting and wild-type xylose-fermenting yeasts.

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유전알고리즘과 겹쳐 그리기 법을 이용한 4절 링크 합성 (Synthesis of 4 bar linkage using genetic algorithm and overlay method)

  • 윤성준;김준환
    • EDISON SW 활용 경진대회 논문집
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    • 제4회(2015년)
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    • pp.476-478
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    • 2015
  • This paper deals with synthesis of 4 bar linkage by using optimum design. To design 4 bar linkage, overlay method is proposed and for optimization, genetic algorithm is applied with objective function. The accuracy of this method will be determined by errors between real value and test value. We will use Chebychev spacing to get 3 precision positions of input angles. The output angles will be determined by the function that the designer wants input and output relations to be. It will be applied to example to show the accuracy of this method. The advantages of using this method are that it is fast to get optimal solution and it is simple to use.

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혼합 위상 정보를 이용한 TTS 합성음 생성 알고리즘 (Speech Synthesis Algorithm Using Mixed Phase Information for TTS Systems)

  • 권철홍;이민규
    • 음성과학
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    • 제8권4호
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    • pp.35-43
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    • 2001
  • New speech synthesis algorithms capable of flexible prosody (especially F0) modification are desired for a high quality TTS system. TD-PSOLA is the most popular synthesis algorithm. The algorithm shows very high quality when F0 modification is limited. However, the quality degradation due to pitch epoch detection error becomes severe as the F0 modification factor becomes large. On the other hand, the vocoder framework is very flexible in F0 manipulation. The synthesized speech quality from the vocoder is far from natural human speech and suffers from buzziness. To remedy the buzzy quality from the vocoder and make more natural synthetic speech, we propose a mixed phase vocoder.

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양자화 진화알고리즘을 적용한 널 패턴합성 알고리즘의 특성 연구 (A Study on Characteristics of Null Pattern Synthesis Algorithm Using Quantum-inspired Evolutionary Algorithm)

  • 서종우;박동철
    • 한국군사과학기술학회지
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    • 제19권4호
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    • pp.492-499
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    • 2016
  • Null pattern synthesis method using the Quantum-inspired Evolutionary Algorithm(QEA) is described in this study. A $12{\times}12$ planar array antenna is considered and each element of the array antenna is controlled by 6-bit phase shifter. The maximum number of iteration of 500 is used in simulation and the rotation angle for updating Q-bit individuals is determined to make the individual converge to the best solution and is summarized in a look-up table. In this study we showed that QEA can satisfactorily synthesize the null pattern using smaller number of individuals compared with the conventional Genetic Algorithm.

면적 제약조건하의 저전력 조합회로 설계를 위한 분할 기반 합성 알고리즘 (A partitioning-based synthesis algorithm for the design of low power combinational circuits under area constraints)

  • 최익성;김형;황선영
    • 전자공학회논문지C
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    • 제35C권7호
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    • pp.46-58
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    • 1998
  • In this paper, we propose a synthesis algorithm for the design of low powe rcombinational circuits under area constraints. The proposed algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reduce unnecessary signal transitions. Partitioning of a given circuit is performed through adaptive simulated annealing algorithm employing the cost function reflecting poer consumption under area constraints. Experimental reuslts for the MCNC benchmark circuits show that the proposed algorithm generates the circuits which consume less power by 61.1% and 51.1%, when compared to those generated by the sis 1.2 and the precomputation algorithm, respectively.

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효율적인 하드웨어 공유를 위한 단어길이 최적화 알고리듬 (A bitwidth optimization algorithm for efficient hardware sharing)

  • 최정일;전홍신;이정주;김문수;황선영
    • 한국통신학회논문지
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    • 제22권3호
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    • pp.454-468
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    • 1997
  • This paper presents a bitwidth optimization algorithm for efficient hardware sharing in digital signal processing system. The proposed algorithm determines the fixed-point representation for each signal through bitwidth optimization to generate the hardware requiring less area. To reduce the operator area, the algorithm partitions the abstract operations in the design description into several groups, such that the operations in the same group can share an operator. The partitioning result are fed to a high-level synthesis system to generate the pipelined fixed-point datapaths. The proposed algorithm has been implemented in SODAS-DSP an automatic synthesis system for fixed-point DSP hardware. Accepting the models of DSP algorithms in schematics, the system automatically generates the fixed-point datapath and controller satisfying the design constraints in area, speed, and SNR(Signal-to-Noise Ratio). Experimental results show that the efficiency of the proposed algorithm by generates the area-efficient DSP hardwares satisfying performance constraints.

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변형기법을 이용한 비동기 시스템의 상위수준 합성기법 (High -Level Synthesis for Asynchronous Systems using Transformational Approaches)

  • 유동훈;이동익
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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    • pp.105-108
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    • 2002
  • Although asynchronous designs have become a promising way to develop complex modern digital systems, there is a few complete design framework for VLSI designers who wish to use automatic CAD tools. Especially, high-level synthesis is not widely concerned until now. In this paper we Proposed a method for high-level synthesis of asynchronous systems as a part of an asynchronous design framework. Our method performs scheduling, allocation, and binding, which are three subtasks of high-level synthesis, in simultaneous using a transformational approach. To deal with complexity of high-level synthesis we use neighborhood search algorithm such as Tabu search.

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