• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2013-2022
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• 1996

Cyclic Codes can be used for burs(or time slot) synchronization as well as error detection as that the overhead bits of the burst, which would be nessary to seperate burst synchronization and error detection systems, may be eliminated. In this paper a new method for combined burst synchronization and error detection is proposed which requires CRC decoding once only, while the previous method which inspects channel error after searching for burst synchronization requeires CRC decoding twice. The proposed method has the advantage of simple implementation and reducing processing time over the previous one, still showing the same detection perfdormance. It may occur that a burst different from the actually transmitted one is falsely accepted in the presence of channel errors. The exact expression for the false acceptance probability is newly presented through a simple derivation basied on the fact that it is determined by channel errors but not by detection methods.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.7
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• pp.443-446
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• 2005

In this paper, we analyses transmission performance of communication security(COMSEC) bit synchronization information over the single channel ground and airborne radion system in variable message format system. Experimental results demonstrate the robust characteristics of the COMSEC bit synchronization information in 10-1 $\~$ 10-5 of bit error channel and the relationship of time duration of bit synchronization and probability of synchronization detection.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.724-730
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• 2017

SpaceWire invented for spacecrafts has Time-Code defined for time synchronization over SpaceWire network. A Time-Code suffers transmission delay of 14[bit-period] and jitter up to 10[bit-period] whenever it passes through a SpaceWire link, which is the primary cause of time synchronization error. This work presents a simple method to improve the time synchronization which uses two extended Time-Codes. Nodes on a SpaceWire network can find how much delay and jitter a received Time-Code has suffered while it passes through the network, and they can correct time synchronization error with this information. The proposed method was validated in a simulation environment developed based on OMNeT++. The simulation result showed that time synchronization error less than a few bit-periods can be achieved. The proposed method is cost effective and suitable for small-scale SpaceWire network systems.

• Journal of the Korea Society for Simulation
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• v.8 no.1
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• pp.77-88
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• 1999

There are two approaches to handle the Causality Error in parallel and distributed simulation. One approach is based on the conservative time synchronization and the other is the optimistic time synchronization. In this paper an efficient null message reduction method for the conservative time synchronization approach is suggested with the experimental results, which could improve performance of simulation and avoid deadlock situations.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.8
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• pp.729-734
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• 2015

Improvement in the control strategy for continuous casting is a crucial requirement to enhance the slab's quality and to increase productivity. The mold oscillator adopts the dual cylinders due to its heavy weight, so the synchronized motion of two cylinders is an important aspect when precise control is needed. The conventional method uses the master-slave control applied to the valve input reference, but the synchronization performance should still be improved. This paper proposes a novel synchronization algorithm for dual cylinders used in a mold oscillator. The master-slave concept is applied to the target reference position, that is, the slave target reference position is controlled to match the slave cylinder's position with the master cylinder's position. In the simulation based on a Simulink model, the proposed algorithm shows a better synchronization performance in aspect of the mean of the absolute error and the peak synchronization error.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.3
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• pp.29-36
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• 2000

It is very import role to increase communication quality that fast detection of random sequence synchronization fail in synchronous stream cipher system using initial synchronization mode. Generally it sends additional information to detect random sequency synchronization fail. But we can't transmit additional informations to decide synchronization fail in a system using RMVD to correct channel error. In this paper we propose a method to detect synchronization fail in the receiver even though a system using RMVD has no margin to send additional information, For detecting random sequency synchronization fail we decipher receiver data analyze probability of transition rate for pre-determined period and decide synchronization fail using calculated transition rate probability. This proposed method is fast very reliable and robust in noisy channel and is easily implemented with hardware.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1477-1486
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• 1997

Conventioally the decoding methods and the design of coset codes for burst synchronization and error detection have been based on the concept that slips occuring to the right or to the left with respect to a reference timing are corrected. In this paper we newly approach to the design of coset codes relying on the condition that only a single code word can exists in an observation interval, which provides an extentended view on the conventional approach. A theorem concerning the condition is presented. A combined burst synchronization and error detection system with maximum slip correction capability have been devised based on the theorem and a detection method is falsely accepted in the presented of channel errors. The false acceptance probabilities of the system are derived and its performance is analyzed through computer computation using the derived results.

• Smart Structures and Systems
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• v.3 no.3
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• pp.299-320
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• 2007

Smart sensors densely distributed over structures can provide rich information for structural monitoring using their onboard wireless communication and computational capabilities. However, issues such as time synchronization error, data loss, and dealing with large amounts of harvested data have limited the implementation of full-fledged systems. Limited network resources (e.g. battery power, storage space, bandwidth, etc.) make these issues quite challenging. This paper first investigates the effects of time synchronization error and data loss, aiming to clarify requirements on synchronization accuracy and communication reliability in SHM applications. Coordinated computing is then examined as a way to manage large amounts of data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.687-694
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• 1999

In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.