• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.515-520
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• 1998

In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1260-1263
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• 2000

Vector control of a single phase induction machine(SPIM) is usually employed by mechanical methods than electrical ones. The disadvantage of a SPIM has large noise at the starting. Using auxiliary winding which is only utilized for starting, the SPIM can be controlled with the vector control method. Regarding a auxiliary winding one phase, the SPIM is analyzed by the unsymmetrical two phase motor and phase transformation is unnecessary such as three phase IM. Including a auxiliary winding, SPIM is modeled by mathematical getting by component of turns ratio with main to auxiliary winding. It will be take with complicated resultant formula, by comparison to symmetrical three phase TM. For using the vector control theory, it must be decoupled of rotor flux and torque component. stator current is controlled and decoupled. This paper presents a variable-speed control system of SPIM, which to decoupled with flux and torque component and to use machine equivalent circuit referred to rotor, conventionally three phase IM by similar method.

• Journal of electromagnetic engineering and science
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• v.6 no.1
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• pp.30-35
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• 2006

This paper describes fully integrated low phase noise MMIC voltage controlled oscillators(VCOs). The Asymmetrical Inductance Tank VCO(AIT-VCO), which optimize the shortcoming of the previous tank's inductance optimization approach, has lower phase noise performance due to achieving higher equivalent parallel resistance and Q value of the tank. This VCO features an output power signal in the range of - 11.53 dBm and a tuning range of 261 MHz or 15.2 % of its operating frequency. This VCO exhibits a phase noise of - 117.3 dBc/Hz at a frequency offset of 100 kHz from carrier. A phase noise reduction of 15 dB was achieved relative to only one spiral inductor. The AIT-VCO achieved low very low figure of merit of -184.6 dBc/Hz. The die area, including buffers and bond pads, is $0.9{\times}0.9mm^2$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.6
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• pp.60-67
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• 2014

Power system fault analysis is commonly based on well-known symmetrical component method, which describes power system elements by positive, negative and zero sequence impedance. The majority of fault in transmission lines is unbalanced fault, such as line-to-ground faults, so that both positive and zero sequence impedance is required for fault analysis. When unbalanced fault occurs, zero sequence current flows through earth and ground wires in overhead transmission systems and through cable sheaths and earth in underground transmission systems. Since zero sequence current distribution between cable sheath and earth is dependent on both sheath bondings and grounding configurations, care must be taken to calculate zero sequence impedance of underground cable transmission lines. In this paper, EMTP-based sequence impedance calculation method was described and applied to 345kV cable transmission systems. Calculation results showed that detailed circuit analysis is desirable to avoid possible errors of sequence impedance calculation resulted from various configuration of cable sheath bonding and grounding in underground cable transmission systems.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1920-1929
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• 2018

In order to provide a source for nine phases suitable for 18-pulse ac to dc power, this paper proposes a new structure for a step-up asymmetrical delta-connected transformer for converting three-phase ac power to nine-phase ac power. The design allows for symmetry between the nine output voltages to improve the power quality of the supply current and to minimize the THD. The results show that this new structure proves the equality between the output voltages with $40^{\circ}-{\alpha}$ and $40^{\circ}+{\alpha}$ phase shifting and produces symmetrical output currents. This result in the elimination of harmonics in the network current and provides a simulated THD that is equal to 5.12 %. An experimental prototype of the step-up asymmetrical delta-autotransformer is developed in the laboratory and the obtained results give a network current with a THD that is equal to 5.35%. Furthermore, a finite element analysis with a 3D magnetic field model is made based on the dimensions of the 4kVA, 400 V laboratory prototype three-phase with three-limb delta-autotransformer with a six-stacked-core in each limb. The magnetic distribution flux, field intensity and magnetic energy are carried out under open-circuit operation or load-loss.

• Journal of the Korea Convergence Society
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• v.12 no.12
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• pp.273-280
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• 2021

This paper presents the results of study of linear oscillating electric machine; Cartesian, cylindrical type with permanent magnet, flux reversal, cylindrical reluctance, and transverse flux type. The focus of the work is the suggestion of the characteristics and design process of propose topology, respectively. First of all, there are five types of the proposed to this study on the basis of the existing literatures; Cartesian type, cylindrical type, flux reversal type, cylindrical reluctance type, and transverse flux type. All topology is achieved using equivalent magnetic circuit considering leakage elements as initial modeling. Cartesian type is investigated by number of phases and number of pole pairs using optimal process. A cylindrical type is described by number of phases and displacement of stroke. The flux reversal type is proposed based on the symmetrical and non symmetrical stator cores of the surface mounted PMs mover, and non slanted PMs and slanted PMs of the flux concentrating PMs mover. A cylindrical reluctance type is studied by the shape of mover teeth in geometric aspect to reduce force ripple and increase magnetic flux. A transverse flux type is considered by dividing the transverse flux electric excited and the transverse flux permanent magnet excited. It is significant that the study gives a design rules and features of linear oscillating electric machine.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.10-21
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• 1999

This paper describes a 12bit CMOS current cell matrix D/A converter which shows a conversion rate of 65MHz and a power supply of 3.3V. Designed D/A converter utilizes current cell matrix structure with good monotonicity characteristic and fast settling time, and it is implemented by using the tree structure bias circuit, the symmetrical routing method with ground line and the cascode current switch to reduce the errors of the conventional D/A converter caused by a threshold voltage mismatch of current cells and a voltage drop of the ground line. The designed D/A converter was implemented with a $0.6{\mu}m$ CMOS n-well technology. The measured data shows a settling time of 20ns, a conversion rate of 50 MHz and a power dissipation of 35.6mW with a single power supply of 3.3V. The experimental SNR, DNL, and INL of the D/A converter is measured to be 55dB, ${\pm}0.5LSB$, and ${\pm}2LSB$, respectively.

• Journal of IKEEE
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• v.16 no.3
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• pp.274-282
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• 2012

In this paper, we propose the design of lighting control algorithm for intelligent LED lighting system. The proposed lighting control algorithm transmitted to MCU through a data bus the environmental information detected from respectively sensor node. The MCU control software was designed to determine the level maintained to depending on the set control method by comparing the results that calculated the dimming level using a signal value. Also, it was designed to be lighting by cross-performed periodically the rotation and reverse method by created fully symmetrical pattern using the control algorithm to LED lighting device. In this paper, the proposed lighting control algorithm improved the reliability of the data sent by designed the system that can be controlled lighting to stable, and it was maintained the event delivery ratio of 91%. Also, the lighting device was decreased the luminous intensity of 32%, the power consumption of 49%, and heat generation of 32%. As a result, it were could be improved the energy efficiency that the life-cycle of LED has been increased 50%.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1111-1116
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• 2011

In this paper, a 60 GHz bidirectional active phase shifter with 130 nm CMOS is presented by replacing CMOS passive switchs in switched-line type phase shifter with Common Gate Amplifier(bidirectional amplifier). Bidirectional active phase shifter is composed of bidirectional amplifier blocks and passive delay line network blocks. The suitable topology of bidirectional amplifier block is CGA(Common Gate Amplifier) topology and matching circuits of input and output are symmetrical due to design same characteristic of it's forward and reverse way. The direction(forward and reverse way) and amplitude of amplification can be controlled by only one bias voltage($V_{DS}$) using combination bias circuit. And passive delay line network blocks are composed of microstrip line. An 1-bit phase shifter is fabricated by Dongbu HiTek 1P8M 130-nm CMOS technology and simulation results present -3 dB average insertion loss and respectively 90 degree and 180 degree phase shift at 60 GHz.