• 전력전자학회논문지
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• 제22권3호
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• pp.185-192
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• 2017

This paper proposes a single-stage interleaved soft-switching electrolytic capacitor-less EV charger with reduced component count and simple circuit structure. The proposed charger achieves ZVS turn-on of all switches and ZCS turn-off of all diodes without regard to voltage and load variation. It achieves high power density even without an input filter due to CCM operation and bulky electrolytic capacitors and without a low-frequency component in the transformer. A 2 kW prototype of the proposed charger with sinusoidal charging is built and tested to verify the validity of the proposed operation.

• 전력전자학회논문지
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• 제21권3호
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• pp.224-230
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• 2016

In this study, a single-power-conversion series-resonant ac-dc converter with high efficiency and high power factor is proposed. The proposed ac-dc converter consists of single-ended primary-inductor converter with an active-clamp circuit and a voltage doubler with series-resonant circuit. The active-clamp circuit clamps the surge voltage and provides zero-voltage switching of the main switch. The series-resonant circuit consists of leakage inductance $L_{lk}$ of the transformer and resonant capacitors $ C_{r1}$ and $ C_{r2}$. This circuit also provides zero-current switching of output diodes $D_1$ and $D_2$. Thus, the switching loss of switches and reverse-recovery loss of output diodes are considerably reduced. The proposed ac-dc converter also achieves high power factor using the proposed control algorithm without the addition of a power factor correction circuit and a dc-link electrolytic capacitor. A detailed theoretical analysis and the experimental results for a 1kW prototype are discussed.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.9-15
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• 2006

이 논문은 코어와 I/O 회로가 포함된 PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks)의 임피던스 변화에 따른 칩의 성능 분석을 나타내었다. I/O 전원에 연결된 코어 전원 잡음이 I/O 스위칭에 어떠한 영향이 미치는지 시뮬레이션 결과를 통하여 보였다. 또한 직접 설계한 $7{\times}5$인치 DLL(Delay Locked Loop)시험 보드를 사용하여 칩의 동작 지점에 따른 전원 잡음의 효과를 분석하였다. $50{\sim}400MHz$에 주파수 대역에 따른 DLL의 지터를 측정하고 시뮬레이션 결과로 얻어진 임피던스 값과 비교하였다. PDN의 공진 피크가 100MHz 주파수에서 1옴보다 큰 임피던스를 갖기 때문에 DLL의 지터는 주파수가 100MHz 근처에서 증가함을 보여준다. 타겟 임피던스를 줄이기 위한 방법인 디커플링 커패시터에 따른 칩과 보드의 임피던스 변화를 보였다. 따라서 전원 공급망 설계는 디커플링 커패시터와 함께 코어 스위칭 전류와 I/O 스위칭 전류를 같이 고려해야 한다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1315-1324
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• 2018

A novel three-phase four-wire inverter topology is presented in this paper. This topology is equipped with a special capacitor balance grid without magnetic saturation. In response to unbalanced load and unequal split DC-link capacitors problems, a qusi-full-bridge DC/DC topology is applied in the balance grid. By using a high-frequency transformer, the energy transfer within the two split dc-link capacitors is realized. The novel topology makes the voltage across two split dc-link capacitors balanced so that the neutral point voltage ripple is inhibited. Under the condition of a stable neutral point voltage, the three-phase four-wire inverter can be equivalent to three independent single phase inverters. As a result, the three-phase inverter can produce symmetrical voltage waves with an unbalanced load. To avoid forward transformer magnetic saturation, the voltages of the primary and secondary windings are controlled to reverse once during each switching period. Furthermore, an improved mode chosen operating principle for this novel topology is designed and analyzed in detail. The simulated results verified the feasibility of this topology and an experimental inverter has been built to test the power quality produced by this topology. Finally, simulation results verify that the novel topology can effectively improve the inhibition of an inverter with a three-phase unbalanced load while decreasing the value of the split capacitor.

• 전력전자학회논문지
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• 제14권5호
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• pp.406-414
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• 2009

본 논문에서는 전원장치의 고집적화와 저가격화를 위해 두 개의 공진커패시터와 두 개의 변압기로 구성된 독립된 공진탱크회로를 갖는 LLC 공진 컨버터를 제안하였다. 제안된 공진회로에 적용된 두개의 변압기는 각 변압기에 흐르는 전류 불평형문제를 저감하기 위해 1차 측은 병렬 연결되어 있고 2차 측은 상호 직렬 연결되어 있다. 300W 시제품을 제작 실험한 결과를 통해 제안된 LLC 공진컨버터가 적용 가능함을 나타냈다.

• 전력전자학회논문지
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• 제22권6호
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• pp.510-516
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• 2017

This paper proposes a single-stage interleaved totem-pole on-board battery charger with a simple structure and a reduced component count. Apart from achieving ZVS turn-on of all switches and ZCS turn-off of all diodes, this charger does not require an input filter due to its CCM operation and bulky electrolytic capacitors, which in turn result in a high power density. A single-stage power conversion technique is applied to the interleaved structure in order to achieve a high power density and high efficiency. A 2.5 kW prototype of the proposed charger is also built and tested to validate the proposed operation.

• Journal of Power Electronics
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• 제17권4호
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• pp.1037-1047
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• 2017

The Differential Power Processing (DPP) converter is a promising multi-module photovoltaic inverter architecture recently proposed for photovoltaic systems. In this paper, a DPP converter architecture, in which each PV-panel has its own DPP converter in shunt, performs distributed maximum power point tracking (DMPPT) control. It maintains a high energy conversion efficiency, even under partial shading conditions. The system architecture only deals with the power differences among the PV panels, which reduces the power capacity of the converters. Therefore, the DPP systems can easily overcome the conventional disadvantages of PCS such as centralized, string, and module integrated converter (MIC) topologies. Among the various types of the DPP systems, the feed-forward method has been selected for both its voltage balancing and power transfer to a modified H-bridge inverter that needs charge balancing of the input capacitors. The modified H-bridge multi-level inverter had some advantages such as a low part count and cost competitiveness when compared to conventional multi-level inverters. Therefore, it is frequently used in photovoltaic (PV) power conditioning system (PCS). However, its simplified switching network draws input current asymmetrically. Therefore, input capacitors in series suffer from a problem due to a charge imbalance. This paper validates the operating principle and feasibility of the proposed topology through the simulation and experimental results. They show that the input-capacitor voltages maintain the voltage balance with the PV MPPT control operating with a 140-W hardware prototype.

• Journal of Power Electronics
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• 제11권4호
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• pp.499-506
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• 2011

This paper presents an interleaved active-clamping zero-voltage-switching (ZVS) forward-flyback converter without an output choke. The presented topology has two active-clamping circuits with two separated transformers. Because of the interleaved operation of the converter, the output current ripple will be reduced. The proposed converter can approximately share the total load current between the two secondaries. Therefore, the transformer copper loss and the rectifier diodes conduction loss can be decreased. The output capacitor is made of two series capacitors which reduces the peak reverse voltage of the rectifier diodes. The circuit has no output inductor and few semiconductor elements, such that the adopted circuit has a simpler structure, a lower cost and is suitable for high power density applications. A detailed analysis and the design of this new converter are described. A prototype converter has been implemented and experimental results have been recorded with an ac input voltage of 85-135Vrms, an output voltage of 12V and an output current of 16A.

• 전력전자학회논문지
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• 제4권6호
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• pp.547-553
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• 1999

본 논문에서는 기존의 12-스텝 인버터에 간단한 보조회로를 추가하여 24-스텝(또는 36-스텝)의 출력파형을 갖는 새로운 방식의 이중접속 멀티스텝 인버터를 제안한다. 제안한 인버터의 보조회로는 두 개의 전압분할용 커패시터, 두 개의 스위칭소자와 저용량의 단권변압기로 구성된다. 이 보조회로의 동작으로 24-스텝의 입·출력 파형을 얻을 수 있으며 한 개의 양방향 스위칭 소자를 추가하면 36-스텝의 파형을 얻게된다. 스위칭 함수를 이용한 전압 및 전류의 분석을 통하여 설계에 필요한 최적의 파라미터를 설정하였다. 제안한 인버터는 PWM방식을 사용할 수 없는 중용량의 SVC등에 적용하면 효과적이다. 본 방식의 타당성을 실험 및 시뮬레이션을 통하여 입증하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.378-381
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• 2002

This paper describes a novel multilevel ad/dc power converter suitable for the protection of frequent output short-circuit. The output dc power of the proposed converter can be disconnected from the load within several hundred microseconds at the instant of short-circuit fault. The rising time of the dc load voltage is as small as several hundred microseconds, and there is no overshoot of the do voltage because the dc output capacitors keep undischarged state. Analysis and simulations are carried out to investigate the operation and usefulness of the proposed scheme.