• Journal of Power Electronics
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• v.18 no.2
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• pp.375-382
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• 2018

A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.37-38
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. It is known that in SiC power MOSFET, the JFET region width is one of the most important parameters. In this paper, we demonstrated that the switching performance of DMOSFET is dependent on the with width of the JFET region by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the n JFET region, CSL, and n-drift layer. It has been found that the JFET region reduces specific on-resistance and therefore the switching characteristics depend on the JFET region.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1639-1649
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• 2016

This paper presents a family of soft-switching DC-DC converters with a simple auxiliary circuit consisting of a coupled winding and a pair of auxiliary switch and diode. The auxiliary circuit is activated in a short interval and thus the circulating conduction losses are small. With the auxiliary circuit, zero-voltage-switching (ZVS) and zero-current-switching are achieved for the main and auxiliary switches respectively, over wide input voltage range and load variation. In addition, the reverse-recovery problem of diodes is significantly alleviated because of the leakage inductor. Furthermore, the coupled inductor simultaneously serves as the main and auxiliary inductors, contributing to reduced magnetic component in comparison with the conventional zero-voltage-transition (ZVT) converters. Experimental results based on a 500 W prototype buck circuit validate the advantages and effectiveness of the proposed magnetic coupling ZVS converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.4
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• pp.268-277
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• 2009

This paper presents an DTC-PWM (Direct Torque Control-Pulse Width Modulation) of PMSM (Permanent Magnet Synchronous Motor). The proposed DTC-PWM method combines a conventional DTC and PWM approach for switching signal generation. The actual torque is estimated by the torque estimator in conventional method, but the switching signal is generated by PWM method according to the switching rules and torque error. A effective voltage vector and zero vector are used to generate the switching signals and asymmetric switching method is applied. A simple calculation of PWM without any complex determination of space vector can assure the constant switching frequency with an constant torque and flux. The proposed torque control scheme for PMSM is verified by experimental results.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.4
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• pp.15-20
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• 1975

The power overshoot is rises in the output during the transient period when the output of nuclear reactor is increased from the initial state to the desired target state and certain amount of constraint on power level is of primary importance for safety control of nuclear reactor. Therefore, the maximum principle is applied to this process control in transfering its power from the initial state(no, co) to the final target state(2no, 2co or 1.5no, 1.5co), adjusting the reactivity so that its overshoot is limited within the allowable constraint required. In this case, the switching points, switching times, optimal lima and optimal control reactivity are calculated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.353-360
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• 2017

Recently, due to physical limitation of Si based power semiconductor, development speed of switching power semiconductors is falling and it is difficult to expect any further performance improvements. SiC based power semiconductor with superior characteristic than Si-based power semiconductor have been developed to overcome these limitations. however, there is not method to apply for real system. Therefore, suggested the feasibility and solution for SiC-based power semiconductor system. design to 1kW class DC-DC boost converter and demonstrated the superiority of SiC MOSFET under the same operating conditions by analyzing switching frequency, duty ratio, voltage and current, and comparing with Si based power semiconductor through experimental efficiency according to each system load. The SiC MOSFET has high efficiency and fast switching speed, and can be designed with small inductors and capacitors which has the advantage of volume reduction of the entire system.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.217-221
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• 2001

This paper presents a new prototype of soft-switching DC-DC power converter with a high frequency transformer link which has two active power controlled switches in full bridge rectifier with capacitor input type smoothing filter. In this DC-DC converter, ZVS of the inverter in transformer primary side and ZCS of active rectifier area in secondary side can be completely achieved by taking advantage of parasitic inductor component of high-frequency transformer and loss less snubbing capacitors. Its operation principle and salient features are described. The steady-state operating characteristics of the proposed DC-DC power converter are illustrated and discussed on the basis of the simulation results in addition to the experimental ones obtained by 2kw-40kHz power converter breadboard set up.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.64-68
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• 2001

This paper presents an innovative prototype of a new conceptual electromagnetic induction heated type far infrared rays radiant heating appliance using the voltage-fed edge-resonant ZVS-PWM high frequency inverter using IGBTs for food cooking and processing which operates under a constant frequency variable power regulation scheme. This power electronic appliance with soft switching high frequency inverter using IGBTs has attracted special interest from some advantageous viewpoints of safety, cleanliness, compactness and rapid temperature response, which is more suitable for consumer power electronics applications.

• ETRI Journal
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• v.30 no.3
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.