• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.59-67
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• 2007

This paper presents a low power dual-level low voltage differential signaling (DLVDS) technique using current source switching for LCD driver ICs in portable products. The transmitter makes dual level signal that has two different level signal 400mVpp and 250mVpp while keeping the advantages of LVDS. The decoding circuit recovers the primary signal from DLVDS. The low power DLVDS is implemented using a $0.25{\mu}m$ CMOS process under 2.5V supply. The proposed circuit shows 800Mbps/2-line data rate and 9mW, 11.5mW power consumptions in transmitter and receiver, respectively. The proposed DLVDS scheme reduce power consumption dramatically compare with conventional one.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.2116-2118
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• 2000

In the technique of Q-switching, very fast electronically controlled optical shutters can be made by using the electro-optic effect in crystals or liquids. The driver for the Pockels cell must be a high-speed, high-voltage switch which also must deliver a sizeable current. Common switching techniques include the use of vacuum tubes, cold cathode tubes, thyratrons, SCRs, and avalanche transistors. Semiconductor devices such as SCRs, avalanche transistors, and MOSFETs have been successfully employed to drive Pockels cell Q-switch. In this study, a simple driver for the Pockels cell Q-switch was developed by using SCRs, pulse transformer and TTL ICs. The Pockels cell Q-switch which was operated by this driver was employed in pulsed Nd:YAG laser system to investigate the operating characteristics of this Q-switch. And we have investigated the output characteristics of this Q-switch as a function of the Q-switch delay time to Xe flashlamp current on.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.463-464
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• 2008

As the demands of LCD and PDP TV are increasing, the high performance HVICs(High Voltage Gate Driver ICs) technology is becoming more necessary. In this paper, we designed the HVIC that has enhanced noise immunity and high driving capability. It can operate at 500KHz switching frequency and permit 600V input voltage. High-side level shifter is designed with noise protection circuit and schmitt trigger. Therefore it has very high dv/dt immunity, the maximum being 50V/ns. The HVIC was designed using $1{\mu}m$ BCD 650V process and verified by Spectre and PSpice of Cadence inc. simulation.

• Smart Structures and Systems
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• v.14 no.4
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• pp.617-641
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• 2014

The energy constraint is still a common issue for the practical application of wireless sensors, since they are usually powered by batteries which limit their lifetime. In this paper, a practical compound energy efficiency strategy is proposed and realized in the implementation of a real time wireless sensor platform. The platform is intended for wireless structural monitoring applications and consists of three parts, wireless sensing unit, base station and data acquisition and configuration software running in a computer within the Matlab environment. The high energy efficiency of the wireless sensor platform is achieved by a proposed adaptive radio transmission power control algorithm, and some straightforward methods, including adopting low power ICs and high efficient power management circuits, low duty cycle radio polling and switching off radio between two adjacent data packets' transmission. The adaptive transmission power control algorithm is based on the statistical average of the path loss estimations using a moving average filter. The algorithm is implemented in the wireless node and relies on the received signal strength feedback piggybacked in the ACK packet from the base station node to estimate the path loss. Therefore, it does not need any control packet overheads. Several experiments are carried out to investigate the link quality of radio channels, validate and evaluate the proposed adaptive transmission power control algorithm, including static and dynamic experiments.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.3
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• pp.48-54
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• 2004

We have developed a new experimental driving system in order to make an easier drive experiment of PDP. By using the system, we can design and simulate the timing of the pulse in computer environment. As a result of the designed timing, we are able to program at PLD(Programmable Logic Device) and control high-voltage FET switches. The new system can reduce the time of the pulse compared with the previous logic gate ICs that realizes switching logic through hardware. In addition, it is a much easier way of changing the timing of the pulse due to the change of the driving method. By using the developed driving system we experimented on two different things- First, the realization of ADS Driving Method that run commonly; Second, gray scale realization on the three electrodes AC PDP.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.4
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• pp.105-109
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• 2018

In this paper, the performance enhancement of a time-modulated array is described. The proposed time-modulated array is based on the topology of a conventional array but uses apodized discrete time switching, instead of phase shifters, to achieve beamforming functions with side-band suppression. Numerical simulations are carried out to examine the performance of this beamforming system based on apodized time sequence of 16 elements linear array. Numerical results reveal that the proposed method provides a more flexible and accurate way of producing desired beampatterns with low or ultralow side-lobe level (SLL) compared with the conventional methods.

• Journal of IKEEE
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• v.11 no.4
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• pp.129-136
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• 2007

In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.567-574
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• 2015

In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.