• Title/Summary/Keyword: Switch port traffic

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The Cell Resequencing Buffer for the Cell Sequence Integrity Guarantee for the Cyclic Banyan Network (사이클릭 벤얀 망의 셀 순서 무결성 보장을 위한 셀 재배열 버퍼)

  • 박재현
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.9
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    • pp.73-80
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    • 2004
  • In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.

Design and Implementation of Content Switching Network Processor and Scalable Switch Fabric

  • Chang, You-Sung;Yi, Ju-Hwan;Oh, Hun-Seung;Lee, Seung-Wang;Kang, Moo-Kyung;Chun, Jung-Bum;Lee, Jun-Hee;Kim, Jin-Seok;Kim, Sang-Ho;Jung, Hee-Jae;Hong, Il-Sung;Kim, Yong-Hwan;Lee, Yu-Sik;Kyung, Chong-Min
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.4
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    • pp.167-174
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    • 2003
  • This paper proposes a network processor especially optimized for content switching. With 2Gbps port capability, it integrates packet processor cluster, content-based classification engine and traffic manager on a single chip. A switch fabric architecture is also designed for scale-up of the network processor's capability over hundreds gigabit bandwidth. Applied in real network systems, the network processor shows wire-speed network address translator (NAT) and content-based switching performance.

Performance Analysis of Demand Assigned Technique for the Multimedia Services via OBP Satellite (OBP(On-Board Processing) 위성의 멀티미디어 서비스를 위한 요구할당 방식의 성능 분석)

  • 김덕년
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.8B
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    • pp.730-738
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    • 2004
  • In this paper, System performance parameters such as throughput, blocking probability and delay have been analyzed and expressed as a function of demanding traffic and service termination, probability, and we centers our discussion at particular downlink port of satellite switch which is capable of switching the individual spot beam and processing the information signals in the packet satellite communications with demand assigned multiple access technique. Delay versus throughput as a function of traffic parameters with several service termination probability can be derived via mathematical formulation and the relative differences of transmission delay is also compared.

Performance of GFR service for TCP traffic in ATM switches with FIFO shared buffer (FIFO 공유 버퍼를 갖는 ATM 스위치에서 TCP 트래픽을 위한 GFR 성능 평가)

  • Park Inyong
    • Journal of Korea Society of Industrial Information Systems
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    • v.10 no.1
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    • pp.49-57
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    • 2005
  • ATM Form has defined the guaranteed frame rate (GFR) service to provide minimum cell rate (MCR) guarantees for TCP traffic in ATM networks and allow it to fairly share residual bandwidth. GFR switch implementation consists of the frame-based generic cell rate algorithm (F-GCRA) and a frame forwarding mechanism. The F-GCRA identifies frames that are eligible for an MCR guarantee. The frame forwarding mechanism buffers cells at a frame unit according to information provided by the F-GCRA and forwards the buffered cells to an output port according to its scheduling discipline. A simple GFR mechanism with shared buffer with a global threshold is a feasible implementation mechanism, but has been known that it is insufficient to guarantee the MCR. This paper has estimated performance of GFR service for TCP traffic over ATM switches with the simple FIFO-based mechanism

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Performance Analysis of Channel Multiple Access Technique for the Multimedia Services via OBP Satellite (OBP(On-Board Processing)위성의 멀티미디어 서비스를 위한 채널 다중접속 방식의 성능 분석)

  • 김덕년;이정렬
    • Journal of the Institute of Convergence Signal Processing
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    • v.2 no.2
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    • pp.83-88
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    • 2001
  • In this paper, System performance parameters such as throughput, blocking probability and delay have been analyzed and expressed as a function of demanding traffic and service terminating probability, and we centers our discussion at particular downlink port of satellite switch which is capable of switching the individual spot beam and processing the information signals in the packet satellite communications with demand assigned multiple access technique. Delay versa throughput as a function of traffic parameters with several service terminating probability can be derived via mathematical formulation and simulation and the relative change of transmission delay was compared.

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A Fairness Control Scheme in Multicast ATM Switches (멀티캐스트 ATM 스위치에서의 공정성 제어 방법)

  • 손동욱;손유익
    • Journal of KIISE:Information Networking
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    • v.30 no.1
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    • pp.134-142
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    • 2003
  • We present an ATM switch architectures based on the multistage interconnection network(MIN) for the efficient multicast traffic control. Many of these applications require multicast connections as well as point-to-point connections. Muiticast connection in which the same message is delivered from a source to arbitrary number of destinations is fundamental in the areas such as teleconferencing, VOD(video on demand), distributed data processing, etc. In designing the multicast ATM switches to support those services, we should consider the fairness(impartiality) and priority control, in addition to the overflow problem, cell processing with large number of copies, and the blocking problem. In particular, the fairness problem which is to distribute the incoming cells to input ports smoothly is occurred when a cell with the large copy number enters upper input port. In this case, the upper input port sends before the lower input port because of the calculating method of running sum, and therefore cell arrived into lower input port Is delayed to next cycle to be sent and transmission delay time becomes longer. In this paper, we propose the cell splitting and group splitting algorithm, and also the fairness scheme on the basis of the nonblocking characteristics for issuing appropriate copy number depending on the number of Input cell in demand. We evaluate the performance of the proposed schemes in terms of the throughput, cell loss rate and cell delay.

The copy networks controlling the copy number according to the fluctuations of the input traffics for an ATM Multicast Switch (입력 트래픽의 특성에 따라 복사 수가 제어되는 ATM 멀티캐스트 스위치 복사 망)

  • Paik, Jung-Hoon;Lim, Chae-Tak
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.10
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    • pp.52-63
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    • 1998
  • In this paper, several improvements to a copy network proposed previously for multicast packet switching are described. The improvements provide a solution to some problems inherent in multicasting. The input fairness problem caused by overf low is solved by a dynamic starting point decider(DSD), which can calculate running sums of copy requests starting from any input port. The starting point is changed adaptively in every time slot based on both the fill level of the input buffers in current time slot and the overflow situations of the previous time slot. Using the fill level of the conventional network. The DSD also provides the function of regulating overall copy requests according to the amount of input traffics. This is an essential function in improving overall throughputs of the copy networks. The throughput of a multicast switch can be improved substantially if partial service of copy request is implemented when overflow occurs. Call-splitting can also be implemented by the DSD in a straightforward manner. The hardware for the DSD is derived with the objective of simple architectures for the high speed operation. Simulation study of the copy network under various traffic conditions is presented to evaluate its performance.

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A Study of the Intelligent Connection of Intrusion prevention System against Hacker Attack (해커의 공격에 대한 지능적 연계 침입방지시스템의 연구)

  • Park Dea-Woo;Lim Seung-In
    • Journal of the Korea Society of Computer and Information
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    • v.11 no.2 s.40
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    • pp.351-360
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    • 2006
  • Proposed security system attacks it, and detect it, and a filter generation, a business to be prompt of interception filtering dates at attack information public information. inner IPS to attack detour setting and a traffic band security, different connection security system, and be attack packet interceptions and service and port interception setting. Exchange new security rule and packet filtering for switch type implementation through dynamic reset memory by real time, and deal with a packet. The attack detection about DDoS, SQL Stammer, Bug bear, Opeserv worm etc. of the 2.5 Gbs which was an attack of a hacker consisted in network performance experiment by real time. Packet by attacks of a hacker was cut off, and ensured the normal inside and external network resources besides the packets which were normal by the results of active renewal.

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Security of Ethernet in Automotive Electric/Electronic Architectures (차량 전자/전기 아키텍쳐에 이더넷 적용을 위한 보안 기술에 대한 연구)

  • Lee, Ho-Yong;Lee, Dong-Hoon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.16 no.5
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    • pp.39-48
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    • 2016
  • One of the major trends of automotive networking architecture is the introduction of automotive Ethernet. Ethernet is already used in single automotive applications (e.g. to connect high-data-rate sources as video cameras), it is expected that the ongoing standardization at IEEE (IEEE802.3bw - 100BASE-T1, respectively IEEE P802.3bp - 1000BASE-T1) will lead to a much broader adoption in future. Those applications will not be limited to simple point-to-point connections, but may affect Electric/Electronic(EE) Architectures as a whole. It is agreed that IP based traffic via Ethernet could be secured by application of well-established IP security protocols (e.g., IPSec, TLS) combined with additional components like, e.g., automotive firewall or IDS. In the case of safety and real-time related applications on resource constraint devices, the IP based communication is not the favorite option to be used with complicated and performance demanding TLS or IPSec. Those applications will be foreseeable incorporate Layer-2 based communication protocols as, e.g., currently standardized at IEEE[13]. The present paper reflects the state-of-the-art communication concepts with respect to security and identifies architectural challenges and potential solutions for future Ethernet Switch-based EE-Architectures. It also gives an overview and provide insights into the ongoing security relevant standardization activities concerning automotive Ethernet. Furthermore, the properties of non-automotive Ethernet security mechanisms as, e.g., IEEE 802.1AE aka. MACsec or 802.1X Port-based Network Access Control, will be evaluated and the applicability for automotive applications will be assessed.