• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.48-55
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• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1184-1195
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• 1998

In this paper, we compare vaious input-buffered ATM switch architectures in structures on input buffer and switching fabric, the resons for performance improvement and degradation, arbitration scheme and maximum throughput, and present comparative merits and demerits of each architecture under random and bursty traffic. We also analyze the prformance of combined architectures of windowing scheme, destination-queueing based input-port expansion schemeand output-port expansion scheme, and show that it is possible to achieve 100% throughput with combined scheme of destination-queueing based input-port expansion scheme and output-port expansio scheme when the number of output group is 2 and output port expansion ratio is 2.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.115-123
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• 2002

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter. The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms. The Proposed switch acquires control over priority transmission through the REQ signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the Proposed switch under uniform traffic conditions.

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.97-105
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• 2003

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The Proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output Port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms . The proposed switch acquires control over priority transmission through the REd signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the proposed switch under non-uniform random traffic conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1755-1764
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• 1997

In this paper, we proposed the mechanism for the buffer allocation and a cell scheduling method with logical separation a single buffer in the ATm switch, and analyzed the cell loss probability and the delay of each trafic (CBR/VBR/ABR) based on the weighted value and the dynamic cell service scheduling algorithm. The proposed switch buffering system classifies composite trafics incoming to the switch, according to the characteristic of traffic, then stores them in the logically separated buffers, and adopts the round-robin service with weighted value in order to transmit cells in buffers though one output port. We analyzed 4 cell service scheduling algorithms with dynamic round-robinfor each logically separated service line of a single buffer, in which buffers have the respective weighted values and 3 classes on mixed traffic which characteristized by traffic descriptor. In simulation, using SIMCRIPT II.5., we model the VBR and the ABR traffics as ON/OFF processes, and the CBR traffic as a Poisson processes. As the results of analysis according to the proposed buffer management mechanism and cell service algorithm, we have found that the required QoS of each VC can be quaranteed depends on a scale of weighted values allocated to buffers that changed the weighted values, and cell scheduling algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1910-1916
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• 1999

This paper suggested to solve ATM switch performance and service rate which was input buffer managed scheme in ATM network with burst traffic characteristics, For this purpose, ATM multiplexer is prepared before sending for handling burst random input traffic to multiplex and then sort based on cell inter-arrival time and cell processing due time which had been marked after that. The server looks for cell header with the most shortest due time and sends it, thus it is satisfied that real time traffic for instance CBR and rt-VBR was guaranteed cell processing time to send fast than non real time traffic. For analysis of ATM switch performance with cell processing due time and priority, each output port has divided into four different virtual buffer and each buffer has assigned different cell inter-arrival time and processing due time according to ATM Forum for example CBT/rt-VBR, nrt-VBR, ABR and UBR and showed it’s optimal service parameters then analyzed service rate behaviors according to each traffic characteristics.

• Journal of Internet Computing and Services
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• v.3 no.3
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• pp.87-93
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• 2002

A complex network and a parallel computer are made up of interconnected switching units. The role of a switching unit is to set up a connection between an input port and an output port, according to the routing information. We proposed our switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. We have analysed the maximum throughput of the revised switch. Our analyses have shown that under the uniform random traffic load, the FIFO discipline is limited to 70%, The switching system consists of an input control unit, a switch unit and an output control unit. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt the new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased by about 11% when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL using Max＋plusII. We also designed our test environment including micro computers, the base station, and the proposed architecture. We proposed a new architecture of the Banyan switch for BISDN networks and parallel computers.

• Journal of the Korea Society of Computer and Information
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• v.8 no.3
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• pp.100-106
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• 2003

This paper presents the design of a value-added ATM switch. The ATM switch ca perform CAC Processing and Firewall Processing Routine at packet-level (IP) at the ATM environment per port. The proposed two routine are integrated into the components of ATM switch. The Firewall switch employs a suggested two routine model to avoid or reduce the latency caused by filtering. Also, we suggest four classes are defined. namely, classes A, B, C, and D, which are orded from the safest to the most dangerous. The suggested model performance of ATM Firewall switch is estimated simulation in terms of the throught and latency by computer.

• KNOM Review
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• v.21 no.2
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• pp.26-34
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• 2018

With the proliferation of cloud computing and services, the internet traffic and the demand for better quality of service are increasing. For this reason, server virtualization and network virtualization technology, which uses the resources of internal servers in the data center more efficiently, is receiving increased attention. However, the existing hardware Test Access Port (TAP) equipment is unfit for deployment in the virtual datapaths configured for server virtualization. Virtual TAP (vTAP), which is a software version of the hardware TAP, overcomes this problem by duplicating packets in a virtual switch. However, implementation of vTAP in a virtual switch has a performance problem because it shares the computing resources of the host machines with virtual switch and other VMs. We propose a vTAP implementation technique based on the extended Berkeley Packet Filter (eBPF), which is a high-speed packet processing technology, and compare its performance with that of the existing vTAP.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.884-887
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• 2002

This paper considers a scheduling problem of routers with VOQ(Virtual Output Queue)s, where the router has an N ${\times}$N port input-queued switch and each input queue is composed of N VOQs. The objective of the paper is to develope scheduling algorithms which minimize mean tardiness under a common due date. The paper characterizes the optimal solution properties. Based upon the characterization, a integer programming is formulated for the optimal solution and two optimal solution algorithms are developed for two special cases of 2 ${\times}$2 switch and N${\times}$N switch with identical traffic.