• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.63-69
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• 2017

This paper presents a highly efficient power management system for UAV-drones. For free from the battery cell-balancing issue, the proposed system allows the drone to utilize a single-cell Li-Po battery. To realize low-voltage input of 3.7V, the switch-mode step-up DC-DC converter is optimally designed with high power efficiency. The prototype DC-DC converter was implemented with an output voltage of 5V, which will be provided to digital parts of the drone. The power efficiency was measured to be max. 91.3% with low surface temperature. The measured line and load regulations were 0.02V/V and 0.15V/A, respectively. Thanks to the proposed power management system, the available time-to-fly of the drone is expected to be significantly extended in virtue of the enhanced power efficiency.

• Journal of Sensor Science and Technology
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• v.21 no.6
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• pp.413-419
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• 2012

A dynamic range extension technique is proposed based on a 3-transistor active pixel sensor (APS) with gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector using a feedback structure. The new APS consists of a pseudo 3-transistor APS and an additional gate/body-tied PMOSFET-type photodetector, and to extend the dynamic range, an NMOSFET switch is proposed. An additional detector and an NMOSFET switch are integrated into the APS to provide negative feedback. The proposed APS and pseudo 3-transistor APS were designed and fabricated using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) process. Afterwards, their optical responses were measured and characterized. Although the proposed pixel size increased in comparison with the pseudo 3-transistor APS, the proposed pixel had a significantly extended dynamic range of 98 dB compared to a pseudo 3-transistor APS, which had a dynamic range of 28 dB. We present a proposed pixel that can be switched between two operating modes depending on the transfer gate voltage. The proposed pixel can be switched between two operating modes depending on the transfer gate voltage: normal mode and WDR mode. We also present an imaging system using the proposed APS.

• Journal of Applied Reliability
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• v.16 no.2
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• pp.162-170
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• 2016

Purpose: The purpose of this study was to analyze the failure modes of an auto transfer switch (ATS), determine the most common failure mechanisms, and iterate the design to improve reliability. Methods: We carried out failure mode and effect analysis (FMEA) to determine the failure modes and mechanisms. We identified the parts or modules that required improvement via two-stage quality function deployment based on FMEA, and improvements to reliability were monitored using the Gomperz growth model. Results: The main failure modes of the ATS were damage to, and deformation of, the stator / movable element due to repetitive movements. Five iterations of design modification were carried out, and the mean time to failure (MTTF) increased to 14,539 cycles, corresponding to 85% of the target MTTF. The Gompertz growth model indicates that the 10th iteration of design modification is expected to achieve the target MTTF. Conclusion: We improved the reliability of mechanical parts via failure mode analysis, and characterized the iterative improvements in the MTTF using the Gompertz growth model.

• Journal of IKEEE
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• v.19 no.3
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• pp.304-310
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• 2015

A SCALDO(Supercapacitor Assisted LDO) regulator is a new regulator having advantages of a SMPS(Switch Mode Power Supply) which has a good efficiency and a LDO(Low Drop-out) regulator which has stable output characteristics and good EMI(Electro Magnetic Interference) characteristics. However, a conventional SCALDO regulator needs a lot of power consumption to control its switches and it drops an efficiency of the circuit. In this paper, to reduce switching power consumption and improve an efficiency of the circuit, a new SCALDO regulator adopting MOSFETs as its switching parts is proposed and it is found out that the proposed SCALDO regulator has the maximum 9.5% higher efficiency than the conventional SCALDO regulator. We also try to simplify production process of the circuit by changing switching control method of the circuit from MCU(Micro-controller unit) based firmware control to hardware control using a comparator and a T-F/F(Flip Flop).

• Journal of IKEEE
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• v.17 no.3
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• pp.267-274
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• 2013

This paper presents a design of LLC resonant converter IC for LED backlight unit based on PFM/PWM dual-mode feedback. Dual output LLC resonant architecture with a single inductor is proposed, where the master output is controlled by the PFM and slave output is controlled by the PWM. To regulate the master output PFM is used as feedback to control the frequency of the power switch. On the other hand, PWM feedback is used to control the pulse width of the power switch and to regulate the slave output. This chip is fabricated in 0.35um 2P3M BC(Bipolar-CMOS-DMOS) Process and the die area is $2.3mm{\times}2.2mm$. Current consumptions is 26mA from 5V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.8
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• pp.610-618
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• 2017

This paper presents a 868/915 MHz CMOS RF transceiver for the ZigBee application. Using a switchless matching network, the off chip switch is removed to achieve the low cost RF transceiver, and by the elimination of the switch's insertion loss we can achieve the benefits for the RF receiver's noise figure and transmitter's power efficiency at the given output power. The receiver is composed of low-noise amplifier, mixer, and baseband analog(BBA) circuit. The transmitter is composed of BBA, mixer, and driver amplifier. And, the integer N type frequency synthesizer is designed. The proposed ZigBee RF full transceiver is implemented on the $0.18{\mu}m$ CMOS technology. Measurement results show that the maximum gain and the noise figure of the receiver are 97.6 dB and 6.8 dB, respectively. The receiver consumes 32 mA in the receiver mode and the transmitter 33 mA in the transmission mode.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.85-94
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• 2002

EMRCA(Explicit Max_min Rate Control Algorithm) switch, which has been proposed in the ATM(Asychronous Transfer Mode) standard, controls the ABR(Available Bit Rate) service traffic in the ATM networks. The ABR service class of ATM networks uses a feedback control mechanism to adapt to varying link capacities. The VS/VD(Virtual Source/Virtual Destination) technique offers the possibility to segment the otherwise end-to-end ABR control loop into separate loops. The improved feedback delay and the control of ABR traffic inside closed segments provide a better performance and QoS(Quality of Service) for ABR connections with respect to throughput, delay, and jitter. This paper is study of an ABR VS/VD flow control method. Linear control theory offers the means to derive correct choices of parameters and to assess performance issues, like stability of the system, during the design phase. The performance goals are a high link utilization, fair bandwidth distribution and robust operation in various environments, which are verified by discrete event simulations. The major contribution of this work is the use of linear control theory to model and design an ABR flow control method tailored for the special layout of a VS/VD switch, the simulation shows that this techniques better than conventional method.

• Journal of Information Technology Applications and Management
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• v.30 no.2
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• pp.45-57
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• 2023

Efforts to build metaverse platform services and expand profit structure are developing in a more realistic direction. The metaverse, which has been centered on 'creation and economy' and 'discovery', will evolve into an 'experience' metaverse, creating tangible business effects where satisfaction with the user experience leads directly to purchase. In this paper, the condition of the avatar used as a medium of economic activity between the metaverse platformer and the user and the business utilization plan were sought. In addition, a new 'metaverse business model' was proposed based on 'experience, discovery, creation and economy', and in particular, it was intended to lay the foundation for the experience metaverse to further develop in the form of 'business experience'. In addition, a survey was conducted on the 'application of metaverse service and avatar' targeting the MZ generation, the main customer base of the current metaverse service. In order to provide a service that satisfies the user, it was concluded that the appearance of the avatar needs to be changed according to the purpose and function. Accordingly, we propose an 'selective switch mode' that can change the avatar's appearance at the desired timing according to the 'experience' and 'purchase purpose' of each metaverse service area. In addition, by strategically utilizing the 'Digilog' psychology, we believe that it will be possible to promote the influx of new users while increasing the loyalty of existing users to the platform. Through the establishment of 'avatar purchase system' by 'selective switch mode' and 'avatar decorating system' by 'digilog' strategy, the experience metaverse, which has been focused on 'digital twin experience' so far, is As it develops into 'business experience', it is expected that the user experience can be further satisfied.

• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1164-1170
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• 2002

In the ACE2000 MPLS system, MPLS Interface Module(MIM) is composed of an ATM Interface Module and a HFMA performing a packet forwarding. In the MIM, the HFMA RSAR receive cells from the Physical layer and reassemble the cells. And the IP Lookup controller perform a packet forwarding after packet classification. Forwarded packet is segmented into cells in the HFMA TSAR and transfer to the ALMA for the transmission to an ATM cell switch. When the MIM make use of an ATM Interface Module, it directly connect the ALMA with a PHY layer using the UTOPIA Level2 interface. Then, an ALMA performs Master Mode. Also, the HFMA TSAR performs the Master Mode in the MIM. Therefore, the UTOPIA-L2 Controller of the Slave Mode require for interfacing between an ALMA and a HFHA TSAR. In this paper, we implement the architecture and cell control mechanism for the UTOPIA-L2 Controller supporting Multi-ports.