• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.258-260
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• 2003

In this paper, we study the reduction of the Dynamic False Contour in a new driving method. This method divides scan lines into Multi Blocks, and drives both selective write and selective erase address. Because of the characteristic of proposed waveform, each scan line has a different sustain pulse weight. Therefore, the Dynamic False Contour occurs seriously in the boundary of each Block. Finally, if scan-lines tie several lines, the Dynamic False Contour can reduce in the boundary of each Block.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1136-1141
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• 1992

This paper proposes a control technique to obtain high frequency quasi sinusoidal DC-Link waveform permitting zero-voltage-switching(ZVS). This operation results in reduction of commutation stress and switching losses in the power devices because they cause no switching loss in principle. But in existing control methods, the resonant capacitor voltage is not frequently made of zero-cross oscillation. We propose an optimum control stratege which can sustain oscillation and keep the capacitor voltage at an allowable level. Some experimental results are included to confirm the validity of the analytical results.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.203-206
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• 2002

In this study, a new driving method is suggested to improve the dark room contrast ratio. The principles of the method are that the reset facing discharges occur between scan and address electrodes instead of surface discharge and that the discharge occurs only for the cells that experienced sustain discharge in preceding sub-field after the first sub-field. The dark room contrast ratio is improved more than 7 times compared with the conventional method.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2016-2018
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• 1999

Until now, there is no report for the relationship between the condition of addressing and the characteristics of surface discharge in ac- PDP. We have known that such experiments were important to drive a-PDP. Therefore, This paper deals with the probability of transfer and the characteristics of luminance according to addressing voltage (Va), blocking voltage (Vg)in addressing period and sustain voltage(Vs)in sustaining period and we use waveform according to ADS (Address and Display period Separation) method.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.96-98
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• 2005

Proposed Multi-level PDP sustain Driver make use of element which has a low voltage rating instead of suggested method by the existing Webber and it passes through a second phase both rising and falling at sustaining voltage waveform In accordance with the change of timing phase(Tr1, Ti1, Tr2) performance comparison of a electric discharge characteristics in a PDP module has been carried out. At the conclusion of experimentation, the feature is extended by alteration of Ti1 and it has little to do with alteration of Tr1.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.123-126
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• 2007

In this study, a high luminous efficacy AC-PDP panel with long discharge gap and grooved dielectric layer has been studied. By applying this high efficacy concept and optimized driving waveform featuring negative biased sustain, ${\sim}2.6lm/W$ of luminous efficacy was achieved in 42- inch HD panel. Modified fabricating process and new discharge cell structure were investigated to obtain improved uniformity and operating characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.391-394
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• 1999

Until now, there is no report for the relationship between the condition of addressing and the characteristics of surface discharge in ac-PDP. We have known that such these experiment was important to drive ac PDP Therefore, this paper deals with the probability of transfer and the character of luminance according to addressing voltage(Va) and blocking voltage(Vg) in addressing period and sustain voltage in sustaining period and we use waveform according to ADS(Address and Display period Separation) method

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.722-725
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• 2003

In AC plasma display, it is very important to quantify the wall voltage induced by the wall charge accumulated on the dielectric surface. If we know the quantities of the wall voltage in each period of every sequence; reset period, address period and sustain period, then it helps us to design the optimal driving waveform for high efficiency plasma display. We develop a new method to measure the wall voltage with VDS (Versatile Driving Simulator) system. From this method the wall voltage induced by a wall charge profiles just after the reset discharge of every cells in plasma display panel can be investigated and analyzed successfully. It is noted that the wall voltage profiles are influenced by the space charge and then they are stabilized as time goes by. It is also noted that both the remaining wall charge at the previous sequence and space charges contribute to wall voltage quantities just after the reset discharge. It is noted that the wall charges contribute dominantly after a few hundreds microseconds, while the space charges have been decayed within 100 ${\mu}s$ just after the reset discharge.