Fabrication Processes of Interconnection Systems for Bare Chip Burn-In Tests Using Epitaxial Layer Growth and Etching Techniques of Silicon (실리콘 에피층 성장과 실리콘 에칭기술을 이용한 Bare Chip Burn-In 테스트용 인터컨넥션 시스템의 제조공정)
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- Journal of the Korean institute of surface engineering
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- v.28 no.3
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- pp.174-181
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- 1995