• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.5
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• pp.365-371
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• 2019

This study shows the feasibility of the parameter of the 1st RC parallel equivalent circuit as a factor of the heat generation of lithium-ion cell. The internal resistance of a lithium-ion cell consists of ohmic and polarization resistances. The internal resistances at various SOCs of the lithium-ion cell are obtained via an electrical characteristic test. The internal resistance is inversely obtained through the amount of heat generated during the experiment. By comparing the resistances obtained using the two methods, the summation of ohmic and polarization resistances is identified as the heating factor of lithium-ion battery. Finally, the amounts of heat generated from the 2C, 3C, and 4C-rate discharge experiments and the COMSOL multiphysics simulation using the summation of ohmic and polarization resistances as the heating parameter are compared. The comparison shows the feasibility of the electrical parameters of the 1st RC parallel equivalent circuit as the heating factor.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1188-1191
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• 2002

A number of studies have recently been published concerning neuron models and asynchronous neural networks. In the case of large-scale neural networks having neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, because of the limitation of the computational power, In this paper, we discuss the circuit structure of a synaptic section model having the spatio-temporal summation of inputs and utilizing CMOS processing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.5
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• pp.295-304
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• 2004

This paper deals with characteristic analysis method using d-q axis equivalent circuit considering iron loss in a single-phase line-start permanent magnet synchronous motor. The iron loss resistance to account for the iron loss is included in the equivalent circuit to improve the modeling accuracy. Furthermore, for the improved calculation of the iron loss, the iron loss is calculated from the magnetic flux density by 2-dimensional finite element method. The result is represented as the iron loss resistance and connected in parallel with the total induced voltage. Therefore, the currents can be expressed as the summation the output current with the current corresponding to the iron loss. Finally, the steady state characteristic analysis results are compared with the experimental results to verify this approach.

• 전기의세계
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• v.24 no.6
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• pp.97-101
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• 1975

The electrical neuronal model described in this paper simulates the most important functional properties of nerve cells. An model circuit incorporating many of the digital and analog properties of neurons is described. Having such properties as variable threshold level, action potential, summation, all-or-none output, absolute and relative refract oriness, and ingibition, it exhibits a considerable amount of functional equivalence to biological structures. This electrical neuronal model has utility not only for studying single unit properties but also for investigating group interactions. Such studies may be relevent to elucidation of neuronal network behavior.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.190-194
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• 2017

Present-day solar panels incorporate inverters as their core components. Switching devices driven by specialized power controllers are operated in a transformerless inverter topology. However, some challenges associated with this configuration include the absence of isolation, causing leakage currents to flow through various components toward ground. This inevitably causes power losses, often being also the primary reason for the power inverters' analog equipment failure. In this paper, various aspects of the leakage currents are studied using different circuit analysis methods. The primary objective is to convert the leakage current energy into a usable DC voltage source. The research is focused on harvesting the leakage currents for producing circa 1.1 V, derived from recently developed rectifier circuits, and driving a $200{\Omega}$ load with a power in the milliwatt range. Even though the output voltage level is low, the harvested power could be used for charging small batteries or capacitors, even driving light loads.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.4
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• pp.403-413
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• 1990

A collision free trajectory control for multiple mobile robots in obstacle-resident workspace is proposed. The proposed method is based on the concept of neural optimization network which has been applied to such problems which are too complex to be handled by traditional analytical methods, and gives good adaptibility for unpredictable environment. In this paper, the positions of the mobile robot are taken as the variables of the neural circuit and the differential equations are derived based on the performance index which is the weighted summation of the functions of the distances between the goal and current position of each robot, between each pair of robots and between the goal and current position of each robot, between each pair of robots and between obstacles and robots. Also is studied the problem of local minimum and of detour in large radius around obstacles, which is caused by inertia of mobile robots. To show the validity of the proposed method an example is illustrated by computer simulation, in which 6 mobile robots with mass and friction traverse in a workspace with 6 obstacles.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.8 no.1
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• pp.38-42
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• 1983

The characteristic of a Tunnel Diode(TD) is approximated by the summation of two exponential terms, obtained from the haracteristic curves displayed on the curve tracer. Using this result, static characteristic of a TD pair was plotted by a computer programming. From these static characteristic curves, the triggering behavior of TC pair multi-vibrators was described graphically. Two stable characteristics were analyzed by piecewise linear Method. Theoritical switching Theoritical switching times of a TD pair flip-flop(F-F) circuits were compared with experimental results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.7 no.2
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• pp.21-25
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• 1970

A Possibility of improving the temperature behavior by the use of a balanced diode compensation circuit in a Digital to Analogue converter is studied. Better linearity is achieved by eliminating the ladder network for the summation by means of an operational amplifier. Speed Consideration are taken to achieve 1.5 mesa bits per second with more than 80% useful plateau.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.6-15
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• 2000

In this paper, we propose a high speed parallel multiplier with a hierarchical architecture using a fast 4-2 compressor and 6-2 compressor. Generally, the performance of parallel multiplier depends on the processing speed of partial products summation tree with CSA adder. In this paper we propose a new circuit of 4-2 compressor and 6-2 compressor which reduces the propagation delay time, compared with conventional one. We Propose a hierarchical multiplier architecture in order to improve the execution speed of 16$\times$16 parallel multiplier using proposed compressors in this paper and make layout design easily by regular structure. The propagation delay time of the proposed 4-2 compressor circuit was 14% reduced as a result of SPICE simulation, compared with the conventional 4-2 compressor. The total propagation delay time of proposed 16$\times$16 parallel multiplier was 12% reduced using proposed 4-2 compressor and 6-2 compressor.