• Title/Summary/Keyword: Successive block

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A New Block Matching Motion Estimation using Predicted Direction Search Algorithm (예측 방향성 탐색 알고리즘을 이용한 새로운 블록 정합 움직임 추정 방식)

  • Seo, Jae-Su;Nam, Jae-Yeol;Gwak, Jin-Seok;Lee, Myeong-Ho
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.2S
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    • pp.638-648
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    • 2000
  • This paper introduces a new technique for block is matching motion estimation. Since the temporal correlation of the image sequence, the motion vector of a block is highly related to the motion vector of the same coordinate block in the previous image frame. If we can obtain useful and enough information from the motion vector of the same coordinate block of the previous frame, the total number of search points used to find the motion vector of the current block may be reduced significantly. Using that idea, an efficient predicted direction search algorithm (PDSA) for block matching algorithm is proposed. Based on the direction of the blocks of the two successive previous frames, if the direction of the to successive blocks is same, the first search point of the proposed PDSA is moved two pixels to the direction of the block. The searching process after moving the first search point is processed according to the fixed search patterns. Otherwise, full search is performed with search area $\pm$2. Simulation results show that PSNR values are improved up to the 3.4dB as depend on the image sequences and improved about 1.5dB on an average. Search times are reduced about 20% than the other fast search algorithms. Simulation results also show that the performance of the PDSA scheme gives better subjective picture quality than the other fast search algorithms and is closer to that of the FS(Full Search) algorithm.

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Performance Analysis of SIC-based Signal Detection Methods in MIMO Systems (순차적 간섭 제거 기반 신호 검출 기법의 성능분석)

  • Yang, Yu-Sik;Kim, Jae-Kwon
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.3
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    • pp.189-196
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    • 2011
  • In this paper, we analyze the error performance of SIC-based signal detection methods in MIMO systems. Considered detection methods are SIC signal detection and LR-SIC signal detection. We derive BLER performance of the methods and the performance is confirmed by computer simulations.

A Fast Block Sum Pyramid Algorithm (빠른 블록 합 피라미드 알고리즘)

  • 정수목
    • The Journal of the Korea Contents Association
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    • v.3 no.4
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    • pp.11-16
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    • 2003
  • In this paper, a Fast Block Sum Pyramid Algorithm (FBSPA) is presented for motion estimation in video coding. PBSPA is based on Block Sum Pyramid Algorithm(BSPA), Efficient Multilevel Successive Elimination Algorithms for Block Matching Motion Estimation, and Fast Algorithms for the Estimation of Motion Vectors. FBSPA reduces the computations for motion estimation of BSPA 29% maximally using partial distortion elimination(PDE) scheme.

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Block-Ordered Layered Detector for MIMO-STBC Using Joint Eigen-Beamformers and Ad-Hoc Power Discrimination Scheme

  • Lee Won-Cheol
    • Journal of Communications and Networks
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    • v.8 no.3
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    • pp.275-285
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    • 2006
  • Suitable for multi-input multi-output (MIMO) communications, the joint beamforming space-time block coding (JBSTBC) scheme is proposed for high-speed downlink transmission. The major functionality of the scheme entails space-time block encoder and joint transmit and receive eigen-beamformer (EBF) incorporating with block-ordered layered decoder (BOLD), and its operating principle is described in this paper. Within these functionalities, the joint EBFs will be utilized for decorrelating fading channels to cause an enhancement in the spatial diversity gain. Furthermore, to fortify the capability of layered successive interference cancellation (LSIC) in block-ordered layered decoding process, this paper will develop a simple ad-hoc transmit power discrimination scheme (TPDS) based on a particular power discrimination function (PDF). To confirm the superior behavior of the proposed JBSTBC scheme employing ad-hoc TPDS, computer simulations will be conducted under various channel conditions with the provision of detailed mathematical derivations for clarifying its functionality.

COMPARISONS OF PARALLEL PRECONDITIONERS FOR THE COMPUTATION OF SMALLEST GENERALIZED EIGENVALUE

  • Ma, Sang-Back;Jang, Ho-Jong;Cho, Jae-Young
    • Journal of applied mathematics & informatics
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    • v.11 no.1_2
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    • pp.305-316
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    • 2003
  • Recently, an iterative algorithm for finding the interior eigenvalues of a definite matrix by CG-type method has been proposed. This method compares to the inverse power method. The given matrices A, and B are assumed to be large and sparse, and SPD( Symmetric Positive Definite) The CG scheme for the optimization of the Rayleigh quotient has been proven a very attractive and promising technique for large sparse eigenproblems for smallest eigenvalue. Also, it is very amenable to parallel computations, like the CG method for the linear systems. A proper choice of the preconditioner significantly improves the convergence of the CG scheme. But for parallel computations we need to find an efficient parallel preconditioner. Our candidates we ILU(0) in the wave-front order, ILU(0) in the multi-coloring order, Point-SSOR(Symmetric Successive Overrelaxation), and Multi-Color Block SSOR preconditioner. Wavefront order is a simple way to increase parallelism in the natural order, and Multi-coloring realizes a parallelism of order(N), where N is the order of the matrix. Another choice is the Multi-Color Block SSOR(Symmetric Successive OverRelaxation) preconditioning. Block SSOR is a symmetric preconditioner which is expected to minimize the interprocessor communication due to the blocking. We implemented the results on the CRAY-T3E with 128 nodes. The MPI (Message Passing Interface) library was adopted for the interprocessor communications. The test problem was drawn from the discretizations of partial differential equations by finite difference methods. The results show that for small number of processors Multi-Color ILU(0) has the best performance, while for large number of processors Multi-Color Block SSOR performs the best.

An Advanced Successive Elimination Algorithm Using Mean Absolute Difference of Neighboring Search Points (경계점의 절대 오차 평균을 이용한 개선된 연속 제거 알고리즘)

  • Jung, Soo-Mok
    • Journal of the Korea Computer Industry Society
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    • v.5 no.5
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    • pp.755-760
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    • 2004
  • In this paper, an advanced successive elimination algorithm was proposed using mean absolute difference of neighboring search points. By using mean absolute difference of neighboring search points, the search point in motion estimation can be eliminated effeciently without matching evaluation that requires very intensive computations. By using adaptive MAD calculation algorithm, the candidate matching block can be eliminated early. So, the number of the proposed algrorithm was verified by experimental results.

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BLOCK LOSS DISTRIBUTION IN AN M/M/1 QUEUE WITH A CELL DISCARDING SCHEME

  • Lee, Gye-Min;Kwag, Min-Kon;Jeon, Jong-Woo;Kim, Chong-Kwon
    • Communications of the Korean Mathematical Society
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    • v.13 no.3
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    • pp.635-642
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    • 1998
  • When an integrated communication system is congested, we may reserve some spaces for non-realtime traffic by discarding a part of realtime traffic. That is sensible because realtime traffic is insensitive to a few losses. Several discarding schemes have been developed including Separate Queue (SQ). Under such schemes, the block loss distribution, i.e., the distribution of the number of losses within a given block which consists of successive data of a type, is important. We derive the block loss distribution of the SQ scheme and modifies the SQ scheme with a threshold.

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Real-time fractal coding implementation using the PC (PC를 이용한 실시간 프랙탈 부호화 구현)

  • 김재철;박종식
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.11
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    • pp.2789-2800
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    • 1996
  • Real time fractal coding for successive QCIF 144*176 luminance images has been implemented on a 50MHz IBM 486 personal computer. To satisfy the frame encoding speed and data compression ratio, following algorithms are adopted. In order to minimize encoding time, extension SAS being not searching of domain blocks is used. for reducing the bits per pixel, conventioal 4*4 range block is extended to 8*8 range block. and range block extension decrease quality of decoded image. For improvement quality of decoded image, the paper apply quad-tree partition mothod. In order to divide **8 range block, self-simiarity is compared 8*8 range block with spatial contractive transformed 8*8 domain block. According to self-simiarity, the block is partitioned and owing to block partition, increased encoding time is minimized. According to self-simiarity of 8*8 range block and spatial contractive transformed 8*8 domain block, number of fractal factor is varied. Simultaneously with minimizing the decrement of decoded image's quality, transmittion rate and encoding time is shorted. The results enable us to process the real-time fractal coding. For the claire test image, the average PSNR was 32.4dB, 0.12 bit rates and 33ms coding time per frame.

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Watermark Algorithm Using Difference Matrix between Successive Blocks (연속 블록간의 화소차이 행렬을 이용한 워터마크 알고리즘)

  • Park, Ki-Hong;Kim, Yoon-Ho
    • Journal of Advanced Navigation Technology
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    • v.12 no.3
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    • pp.273-279
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    • 2008
  • In this paper, we proposed a watermarking algorithm by using difference matrix between successive blocks in the transform domain. In the preprocessing, original image is decomposed with 1-level sub-bands by DWT. Then, all sub-bands which are excepted the low-frequency bands are set to normalize and make a reference image after transforming inverse DWT. The statistic variance of successive blocks between the original image and the reference image are calculated and finally, watermark is embedded considering the local characteristic with respect to the high-frequence components. Experimental results showed that the proposed approach is robust and better invisible in such attacks as filtering, JPEG and noise addition.

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Low Power SAR ADC with Series Capacitor DAC (직렬 커패시터 D/A 변환기를 갖는 저전력 축차 비교형 A/D 변환기)

  • Lee, Jeong-Hyeon;Jin, Yu-Rin;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.68 no.1
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    • pp.90-97
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    • 2019
  • The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.