• 대한전자공학회논문지
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• 제25권2호
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• pp.182-187
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• 1988

Hot carrier induced device degradation characteristics under DC bias stress have been investigated in n-MOSFETs with channel length of 1.2,1.8 um, and compared with those of LDD structure device with same channel length. Based on these results, the device lifetime in normal operating bias(Vgs=Vds=5V) is evaluated. The lifetimes of conventional and LDD n-MOSFET with channel length of 1.2 um are estimated about for 17 days and for 12 years, respectively. The degradation rate of LDD n-MOSFET under the same stress is the lowest at n-region implnatation dose of 2.5E15 cm-\ulcorner while the substrate current is the lowest at the dose of 1E13cm-\ulcorner Thses results show that the device degradation characteristics are basic measurement parameter to find optimum process conditions in LDD devices and evaluate a reliability of sub-micron device.

• 대한전자공학회논문지
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• 제24권3호
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• pp.472-477
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• 1987

In order to prevent the short-channel effects due to threshold voltage adjustment implantation in conventional n+ doped silicon gate process, a new approach involving automatic doping of polycide by boron during source and drain implantation is introduced. P-MOSFET devece fabricated by theis approach shows improved short channel characteristics than conventional device with n+ doped gate. Some concerns of adopting this approach in CMOS technology are addressed togetheer with some suggestions.

• 전자공학회논문지A
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• 제33A권12호
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• pp.65-71
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• 1996

A novel lateral field emitter triode has been designed and fabricated. It has self-vacuum environmets and low turn-on voltage, so that the chief problems of previous field emission devices such as additional vacuum sealing process and high turn-on voltage are settled. An in-situ vaccum encapsulation empolying recessed cavities by isotropic RIE (reactive ion etch) method and an electron beam evaporated molybdenum vacuum seals are implemented to fabricate the new field emitter triode. The device exhibits low turn-on voltage of 7V, stabel current density of 2.mu.A/tip at V$_{AC}$ = 30V, and high transconductance (g$_{m}$) of 1.7$\mu$S at V$_{AC}$ = 22V. The superb device characteristics are probably due to sub-micron dimension device structure and the pencil type lateral cathode tip employing upper and lower LOCOS oxidation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• 한국진공학회지
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• 제6권1호
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• pp.20-27
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• 1997

0.25$\mu\textrm{m}$이하의 최소선폭을 같는 초고집적회로에 사용할 수 있는 구리박막의 형성기술 을 조사하였다. 본 실험에서는 측면박막 형성에 적합한 화학적 증착을 시도하였으며 (hfac)Cu(VTMS)(hexafluoroacetylacetonate vinyltrimethylisilane copper(I))로 명명된 금속 유기 화합물을 원료로 사용하였다. 구리박막의 형성은 TiN와 $SiO_2$모재 위에 이루어 졌으며, 형성 중에 모재의 온도와 증착용기 내 압력의 함수로서 집적회로 공정상 주요 변수인 박막 의 비저항, 박막의 증착선택도를 측정하였다. 구리박막은 모재온도 $180^{\circ}C$와 증착용기의 압력 0.6Torr의 조건에서 가장 좋은 전기적 성질을 보여 주었다. 이 조건에서 형성된 구리박막은 다결정 구조를 나타내었으며 구리박막의 증착속도는 120nm/min, 비저항은 0.25$mu \Omega$.cm, 평균거칠기는 15.5nm로서 0.25$\mu\textrm{m}$이하 선폭의 집적회로에서 요구되는 전기적, 재료적 사양에 근접한 구리박막을 얻었다. 또한 140-$250^{\circ}C$의 모재 온도 범위에서 TiN모재와 $SiO_2$모재 사 이에 뚜렸한 증착선택성이 관측되었다.

• 한국정밀공학회지
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• 제16권2호통권95호
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• pp.74-81
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• 1999

The integrated chip of optical micro-encoder was fabricated and the feasibility as displacement measurement device was confirmed. The geometry of micro-encoder was designed to utilize the optical interference effect on the second order of diffracted beams. The hybrid-type micro-encoder consisted with light emitting diode, photodiode, polyimide wave-guide and micro-lens provides stable micro-encoding results for high speed displacements. The measurement shows the resolution of displacement of 1.00 +/- 0.02 ${\mu}m$ for the grating with scale pitch of 2.0${\mu}m$.

• 한국결정성장학회지
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• 제14권2호
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• pp.47-49
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• 2004

Gate protection $SiN_x$ as an alternative to a conventional re-oxidation process in Dynamic Random Access Memory devices is investigated. This process can not only protect the gate electrode tungsten against oxidation, but also save the thermal budget due to the re-oxidation. The protection $SiN_x$ process is applied to the poly-Si gate, and its device performance is measured and compared with the re-oxidation processed poly-Si gate. The results on the gate dielectric integrity show that etch damage-curing capability of protection $SiN_x$ is comparable to the re-oxidation process. In addition, the hot carrier immunity of the $SiN_x$ deposited gate is superior to that of re-oxidation processed gate.

• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.157-164
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• 1994

DRAM(Dynamic Random Access Memory)은 반도체 소자중 가장 대표적인 기억소자로, switch역활을 하는 1개의 transistor와 data의 전하를 축적하는 1개의 capacitor로 구성된 단순한 구조와 고집적화에 용이하다는 이점을 바탕으로, supercomputer에서 가전제품 및 산업기기에 이르기 까지 널리 이용되어왔다. 한편으로 DRAM사업은 고가의 장치사업으로 조기시장 진입을 위하여 초기에 막대한 자본투자, 급속한 기술발전, 짧은 life cycle, 가격급락등이 심하여, 시한내 투자회수가 이루어져야 하는 위험도가 큰 기회사업이라는 양면성도 가지고 있다. 이러한 관점때문에 새로운 DRAM기술은 매 세대마다 끊임없이 빠른 속도로 개발되어왔다. 그러나 sub-micron이하의 DRAM세대로 갈수록 그에 대한 신기술은 점차 어렵게 되어가고, 한편으로는 system의 다양화에 따른 요구도 강하여, 이제는 통상적인 DRAM의 고집적화/저가의 전략만으로는 생존하기 어려운 실정이므로 개발전략도 수정하여야만 할 것이다. 이러한 어려운 기술한계를 극복하기 위하여 새로운 소자기술 및 공정개발에 대한 breakthrough가 이루어져야 할 것이다. 이러한 관점에서 현재까지의 DRAM개발 추이와 향후의 기술방향에 관하여 몇가지 중요한 item을 설정하여 논의해 보기로 한다.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.687-690
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• 2003

Experimental results are presented for gate oxide degradation and its effect on device parameters under negative and positive bias stress conditions using NMOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both hole- and electron-trapping are found to dominate the reliability of gate oxide. However, with changing gate voltage polarity, the degradation becomes dominated by electron trapping. Statistical parameter variations as well as the "OFF" leakage current depend on those charge trapping. Our results therefore show that Si or O bond breakage by electron can be another origin of the investigated gate oxide degradation.gradation.