• 대한전자공학회논문지
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• 제24권3호
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• pp.472-477
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• 1987

In order to prevent the short-channel effects due to threshold voltage adjustment implantation in conventional n+ doped silicon gate process, a new approach involving automatic doping of polycide by boron during source and drain implantation is introduced. P-MOSFET devece fabricated by theis approach shows improved short channel characteristics than conventional device with n+ doped gate. Some concerns of adopting this approach in CMOS technology are addressed togetheer with some suggestions.

• Journal of Electrical Engineering and information Science
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• 제2권5호
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• Transactions on Electrical and Electronic Materials
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• 제3권3호
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• pp.14-17
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• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.134-138
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• 2008

We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudo-random manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.157-164
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• 1994

DRAM(Dynamic Random Access Memory)은 반도체 소자중 가장 대표적인 기억소자로, switch역활을 하는 1개의 transistor와 data의 전하를 축적하는 1개의 capacitor로 구성된 단순한 구조와 고집적화에 용이하다는 이점을 바탕으로, supercomputer에서 가전제품 및 산업기기에 이르기 까지 널리 이용되어왔다. 한편으로 DRAM사업은 고가의 장치사업으로 조기시장 진입을 위하여 초기에 막대한 자본투자, 급속한 기술발전, 짧은 life cycle, 가격급락등이 심하여, 시한내 투자회수가 이루어져야 하는 위험도가 큰 기회사업이라는 양면성도 가지고 있다. 이러한 관점때문에 새로운 DRAM기술은 매 세대마다 끊임없이 빠른 속도로 개발되어왔다. 그러나 sub-micron이하의 DRAM세대로 갈수록 그에 대한 신기술은 점차 어렵게 되어가고, 한편으로는 system의 다양화에 따른 요구도 강하여, 이제는 통상적인 DRAM의 고집적화/저가의 전략만으로는 생존하기 어려운 실정이므로 개발전략도 수정하여야만 할 것이다. 이러한 어려운 기술한계를 극복하기 위하여 새로운 소자기술 및 공정개발에 대한 breakthrough가 이루어져야 할 것이다. 이러한 관점에서 현재까지의 DRAM개발 추이와 향후의 기술방향에 관하여 몇가지 중요한 item을 설정하여 논의해 보기로 한다.

• 한국재료학회지
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• 제1권3호
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• pp.132-138
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• 1991

2충의 BPSG를 사용하는 서브마이크론 CMOS DRAM에 있어 전기적 특성에 관한 BPSG flow온도의 영향을 비교하였다. BPSG flow온도를 $850^{\circ}C/850^{\circ}C,\;850^{\circ}C/900^{\circ}C,\;900^{\circ}C/900^{\circ}C$의 3가지 다른 조합을 적용하여 문턱전압, 파괴전압, Isolation전압과 더불어 면저항과 접촉 저항을 조사하였다. $900^{\circ}C/900^{\circ}C$ flow의 경우 NMOS에서 문턱전압은 $0.8\mu\textrm{m}$ 미만의 채널길이에서 급격히 감소하나 PMOS 경우는 차이가 없었다. NMOS와 PMOS의 파괴전압은 각각 $0.7\mu\textrm{m}$와 $0.8\mu\textrm{m}$ 이하에서 급격히 감소하였다. 그러나 $850^{\circ}C/850^{\circ}C$ flow의 경우에는 NMOS와 PMOS모두 문턱전압과 파괴전압은 채널길이 $0.7\mu\textrm{m}$까지 감소하지 않았다. Isolation전압은 BPSG flow온도 감소에 따라 증가하였다. 면저항과 접촉 저항은 BPSG flow온도가 $900^{\circ}C$에서 $850^{\circ}C$로 감소됨에 따라 급격히 증가되었다. 이와 같은 결과는 열처리 온도에 따라 dopant의 확산과 활성화에 관련 있는 것으로 생각된다. 접촉 저항 증가에 대한 개선 방법에 대하여 고찰하였다.

• 한국전기전자재료학회논문지
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• 제23권6호
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• pp.431-435
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• 2010

In this paper, we investigated the dependence of device performance and hot carrier lifetime on the channel direction of PMOSFET. $I_{D.sat}$ vs. $I_{Off}$ characteristic of PMOSFET with <100> channel direction is greater than that with <110> channel direction because carrier mobility of <100> channel direction is greater than that of <110> channel direction. However, hot carrier lifetime for <110> channel direction is much lower than that with <110> channel due to the greater impact ionization rate in the <100> channel direction. Therefore, concurrent consideration of reliability characteristics and device performance is necessary for channel strain engineering of MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.