• Tribology and Lubricants
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• 제5권2호
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• pp.68-76
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• 1989

In this paper, the influence of ram-pressure on the static and dynamic characteristics of infinite width tilting-pad journal bearing is investigated theoretically. The ram-pressure is obtained by assumption of conservation of mechanical energy of the lubricant flow through the leading edge of the pad. The pressure in the lubricating film is numerically calculated using the ram-pressure obtained as the inlet pressure boundary condition of the pad. The static equilibrium state of tilting-pad journal bearing is determined by Newton-Raphson iteration method. A numerical results are presented in graphic form and relationships between the ram-pressure and the static and dynamic characteristics are discussed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.659-660
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• 2006

The low crosstalk row-decoder is studied for PoRAM applications. Because polymer-based memories can be more densely integrated than established silicon-based ones, PoRAM is highly sensitive for the crosstalk problem. To overcome the problem and to suggest the suitable decoder for PoRAM, this paper shows the comparison of the row-path characteristics for both the 2-stage dynamic logic decoder and the 2-stage static logic decoder. Moreover, to suppress the Glitch effect which is observed by using the static logic decoder, the Master-Slave(M/S) D-Flip/Flop(D-F/F) is applied as a deglitch. Finally, the improved output result of the 2-stage static logic decoder with the M/S D-F/F is shown..

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권4호
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• pp.199-203
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• 2006

This paper presents an ASER (Accelerated Soft Error Rate) integral model. The model is based on the facts that the generated EHP/s(electron hole pairs) are diminished after some residual range of the incident alpha particle, where residual range is a function of the incident angle and the capping layer thickness over the semiconductor junction. The ASER is influenced by the flux of the alpha particles, the junction area ratio, the alpha particle incident angle when the critical charge is same as the collected charge, and the sizes of the alpha source and the chip. The model was examined with 8M static RAM samples. The measured ASER data showed good agreement with the calculated values using the model. The ASER decreased exponentially with respect to the operational voltage. As the capping layer thickness increases up to $16{\mu}m$, the ASER increases, and after that thickness, the ASER decreases. The ASER increased as the depth of BNW increased from $0{\mu}m\;to\;4{\mu}m$. and then saturated. The ASER decreased as the node capacitance increased from 2fF to 5fF.

• 한국통신학회논문지
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• 제35권6B호
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• pp.948-953
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• 2010

본 논문에서는 슈퍼스칼라 구조를 가진 시스템의 명령어 캐시에서 효율적으로 소프트오류를 검출할 수 있는 기법을 제안한다. 명령어 캐시로 주로 사용되는 고속 정적 RAM(Random Access Memory)에 적용할 수 있으며 1D 패리티와 인터리빙을 통해 기존 기법들과 비교하여 더 적은 메모리 오버헤드로 연집오류를 검출할 수 있다. 정적 RAM에서는 소프트오류의 발생만을 확인하고 검출된 소프트오류의 정정은 명령어 캐시의 캐시 미스와 같이 처리하여 하위 메모리로부터 명령어들을 다시 인출하는 방식이다. 이를 통해 명령어 캐시의 성능에 영향을 주지 않으면서 연집오류를 검출하고 정정할 수 있으며 최대 4$\times$4의 윈도우 내에서 발생된 연집오류를 검출 할 수 있다. 제안된 방식을 이용하면 256비트 $\times$ 256비트 크기의 메모리에서 기존의 4-way 인터리빙 기법에서 검출에 필요한 패리티 크기의 25%만으로도 동일한 4비트의 연집오류를 검출 할 수 있다.

• International Journal of Reliability and Applications
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• 제2권4호
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• pp.269-280
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• 2001

The objective of this paper is to provide a model for effective implementation of costing RAM management in the design and procurement of production facility considering the system cost-performance trade-off. This research proposes a two-step approach of costing RAM design and test of system RAM for production facility. In Step 1, a static model is proposed to find an initial system configuration to meet the required performance based on system RAM and LCC and analyzes the trade-off relationships between various factors of RAM and LCC. In the second Step, we developed time and failure truncated models for system reliability test and analysis. For the computational purpose, we developed computer programs and have shown the sample results. By the sample test run, the proposed model has shown the possibilities to provide a good method to analyze system performance evaluation for both design and operational phase, This model can be applied to a wide variety of systems not only for costing RAM of the production facilities but also for the other kinds of equipment.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권3호
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• pp.111-115
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• 2006

We investigated accelerated soft error rate(ASER) in 8M static random access memory(SRAM) cells. The effects on ASER by well structure, operational voltage, and cell transistor threshold voltage are examined. The ASER decreased exponentially with respect to operational voltage. The chips with buried nwell1 layer showed lower ASER than those either with normal well structure or with buried nwell1 + buried pwell structure. The ASER decreased as the ion implantation energy onto buried nwell1 changed from 1.5 MeV to 1.0 MeV. The lower viscosity of the capping layer also revealed lower ASER value. The decrease in the threshold voltage of driver or load transistor in SRAM cells caused the increase in the transistor on-current, resulting in lower ASER value. We confirmed that in order to obtain low ASER SRAM cells, it is necessary to also the buried nwell1 structure scheme and to fabricate the cell transistors with low threshold voltage and high on-current.

• 전자진흥
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• 제7권12호
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• pp.50-55
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• 1987

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.23-25
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• 1996

In this paper aims at studying the minimal test pattem of the RAM. This also propose a scheme of testing faults from the new fault model using the LLB. The length of test patterns are 6N(1-wsf), 9.5N(2-wsf), 7N(3-wsfl, 3N(4-wsf) operations in N-bit RAM. This test techniques can write into memory cell the number of write operations is reduced and then much testing time is saved. A test set which detects all positive-negative static t-ws faults for t=0, 1, 2, 3, 4 and detects all pattern sensitive fault in memory array. A new fault model, which encompasses the existing fault model Is proposed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1206-1208
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• 1993

This paper is to study and realize a measuring device for complex dielectric constants. The device is consisted in order of interface unit, external RAM, programmable counter, D/A converter, measuring circuit, Sample & Hold circuit, A/D converter and related control circuits. Various excitation waves are digitalized and sent to the 4096 static RAM by personal computer. These data saved in the RAM are converted to analog excitation waves through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM according to clock pulses. Such generated waves are applied to dielectrics under test and their responses are sampled and converted to digital data through A/D converter. The computer takes the digital data and calculates finally the complex dielectric constants. The frequencies for Measurement ranges from 0.04 Hz to 10 kHz.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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• pp.2493-2502
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• 2011

소프트웨어 RAMS를 위한 소프트웨어 코드의 정적 분석을 위해서 경험 있는 테스터들은 안전에 고장을 야기시키는 정적 기법을 선별적으로 사용하여 결함을 검출하기를 선호한다. 코딩 규칙, 소프트웨어 메트릭스, 위험데이터 등의 정적 기법들의 많은 사례들이 보고되고 있다. 그러나 다수의 분석 사례들은 정적 분석의 효과를 이론적으로만 제시할 뿐, 코드 분석에 사용된 코드 결함들을 테스터가 어떻게 판단하여 분류하고 이를 높은 품질을 보증하기 위해 올바르게 제거 수정하였는가에 대한 구체적인 설명이 부족하다. 간혹, 일부 사례를 통해서 그 효과를 제시하는 자료들도 있으나 그 적용과정이 구체적이지 않아 신뢰를 얻기가 어려운 경우가 많다. 본 논문에서는 안전성 화보를 위해 철도분야에서 많이 사용되는 정적 기법들을 소개하고 이들을 실제 개발 과제에 적용하여 각각의 결과를 비교하고 분석하였다. 본 논문의 결과를 일반화하기는 어려울 것이지만 하나의 사례 연구로서 참고하고 활용될 수 있을 것이다.