• The Journal of the Acoustical Society of Korea
• /
• v.12 no.1
• /
• pp.27-36
• /
• 1993

FM방식의 악기음원합성은 해당 악기의 음색과 음정에 맞는 FM의 기본 주파수와 변조 계수를 정하여 신호 파형을 생성하는 것으로, 다른 가, 감산방식 또는 PCM방식 등에 비해 비교적 간단한 구조로 다양한 악기음원합성이 가능하다. 따라서 현재 사용되고 있는 개인용 컴퓨터에 부착되는 사운드합성 카드에는 FM방식 음원합성기술이 적용되고 있다. 본 논문에서는 FM방식 음원합성기술을 이용하여 실시간 악기음원합성이 가능한 논리회로를 설계하는데 관한 연구를 기술한다. 본 연구에서는 소프트웨어 프로그래밍에 의해 FM방식 음원합성기의 구조를 설계하고 주요 블록의 최적 변수 값을 실험하였다. 논리회로 설계 및 회로검증은 향후 주문형반도체(ASIC:Application Specific Integrated Circuit)제작을 위해 기존의 표준셀 라이브러리와 주문형반도체 전용 설계시스템을 사용하였다. 회로검증 결과는 간이 평가보드를 제작하고 PC와 접속시켜 생성된 악기음을 직접듣는 주관적 평가방법으로 최종 확인하였다.

• International Journal of Internet, Broadcasting and Communication
• /
• v.5 no.2
• /
• pp.11-14
• /
• 2013

This paper describes the sigma-delta ADC/DAC digital block with two channels. The ADC block has comb filter and three half band filters. And the DAC block has 5th Cascaded-of-Integrators Feedback DSM. The ADC and DAC support I2S, RJ, LJ and selectable input data modes of 24bit, 20bit, and 16bit. It is fabricated with 0.35um Hynix standard CMOS cell library. The chip size is 3700*3700um. It has been verified using NC Verilog Simulator and Matlab Tool.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.11
• /
• pp.2978-2990
• /
• 1996

With the advent of multimedia era, there are ever increasing interest in computer music and sound syntheis. An FM type sound synthesizing method makes possible the syntheis ofvarious sounds ofmusical instruments with a relatively simple hardware architecture. Therefore, in this paper, we designed a hardware architecture for real-time sound synthesizer and its logic gates. In this paper, we designed a basic sound generator for implementation of real-time logic gates, analzed characteristics of sounds synthesized in this architecture and extracted parameters of FM sounds of musical instruments by using the Csound software. The major bolkcs to build the hardware are a phase-generator, a singe-function-generator, an envelope-generator and a multiplier-part. Finally, logic circuits are designed and verified in VHDL and logic gates by 1.0um standard cell library, which will be easily implementable by the form of ASIC.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.541-542
• /
• 2008

We propose an architecture for a lighting engine for mobile 3D graphics. The proposed architecture has a variable pipeline depending on lighting effects and the number of lighting sources so that unnecessary operations and power consumption are minimized. We design a lighting engine basedon the proposed architecture using Verilog-HDL and synthesized it using a 0.25um CMOS standard cell library at 100MHz. The synthesis results show that it occupies 180,000 and 260,000 gates for 24bit and 32bit formats, respectively.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.349-352
• /
• 2000

In this paper, a SIMD 64bit MAC (Multiply -Accumulate) unit is designed. It is composed of two 32bit MAC unit which supports SIMD 16bit operations. As a result, It can process two 32bit MAC operations or four 16bit operations in one cycle. Proposed MAC unit is described in Verilog HDL. After functional verification is performed, MAC unit is synthesized and optimized with 0.35$\mu\textrm{m}$ standard cell library. The synthesis result shows that this MAC unit can operate at 80㎒ of clock frequency in 85$^{\circ}C$, 3.0V, worst case process and 125㎒ of clock frequency at 25$^{\circ}C$, 3.3V, typical case process. It achieves 320Mops of performance, and is suitable for embedded DSP processors.

• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.83-86
• /
• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.10
• /
• pp.1-7
• /
• 1997

This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

• ETRI Journal
• /
• v.24 no.5
• /
• pp.391-397
• /
• 2002

This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 ${\mu}m$ standard cell library, and then verified the functions thoroughly.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.321-324
• /
• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• IEIE Transactions on Smart Processing and Computing
• /
• v.3 no.6
• /
• pp.353-357
• /
• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.